Lucian Paul-Trifu | 5ee4f4e | 2022-06-22 18:45:30 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLAT_DRTM_H |
| 8 | #define PLAT_DRTM_H |
| 9 | |
johpow01 | baa3e6c | 2022-03-11 17:50:58 -0600 | [diff] [blame] | 10 | #include <stdint.h> |
| 11 | #include <lib/xlat_tables/xlat_tables_compat.h> |
| 12 | |
| 13 | typedef struct { |
| 14 | uint8_t max_num_mem_prot_regions; |
| 15 | uint8_t dma_protection_support; |
| 16 | } plat_drtm_dma_prot_features_t; |
| 17 | |
| 18 | typedef struct { |
| 19 | bool tpm_based_hash_support; |
| 20 | uint32_t firmware_hash_algorithm; |
| 21 | } plat_drtm_tpm_features_t; |
| 22 | |
| 23 | typedef struct { |
| 24 | uint64_t region_address; |
| 25 | uint64_t region_size_type; |
| 26 | } __attribute__((packed)) drtm_mem_region_t; |
| 27 | |
| 28 | /* |
| 29 | * Memory region descriptor table structure as per DRTM beta0 section 3.13 |
| 30 | * Table 11 MEMORY_REGION_DESCRIPTOR_TABLE |
| 31 | */ |
| 32 | typedef struct { |
| 33 | uint16_t revision; |
| 34 | uint16_t reserved; |
| 35 | uint32_t num_regions; |
| 36 | drtm_mem_region_t region[]; |
| 37 | } __attribute__((packed)) drtm_memory_region_descriptor_table_t; |
| 38 | |
| 39 | /* platform specific address map functions */ |
| 40 | const mmap_region_t *plat_get_addr_mmap(void); |
| 41 | |
Lucian Paul-Trifu | 5ee4f4e | 2022-06-22 18:45:30 +0100 | [diff] [blame] | 42 | /* platform-specific DMA protection functions */ |
| 43 | bool plat_has_non_host_platforms(void); |
| 44 | bool plat_has_unmanaged_dma_peripherals(void); |
| 45 | unsigned int plat_get_total_smmus(void); |
| 46 | void plat_enumerate_smmus(const uintptr_t **smmus_out, |
| 47 | size_t *smmu_count_out); |
johpow01 | baa3e6c | 2022-03-11 17:50:58 -0600 | [diff] [blame] | 48 | const plat_drtm_dma_prot_features_t *plat_drtm_get_dma_prot_features(void); |
| 49 | uint64_t plat_drtm_dma_prot_get_max_table_bytes(void); |
| 50 | |
| 51 | /* platform-specific TPM functions */ |
| 52 | const plat_drtm_tpm_features_t *plat_drtm_get_tpm_features(void); |
| 53 | |
| 54 | /* |
| 55 | * TODO: Implement these functions as per the platform use case, |
| 56 | * as of now none of the platform uses these functions |
| 57 | */ |
| 58 | uint64_t plat_drtm_get_min_size_normal_world_dce(void); |
| 59 | uint64_t plat_drtm_get_tcb_hash_table_size(void); |
| 60 | uint64_t plat_drtm_get_imp_def_dlme_region_size(void); |
| 61 | uint64_t plat_drtm_get_tcb_hash_features(void); |
Lucian Paul-Trifu | 5ee4f4e | 2022-06-22 18:45:30 +0100 | [diff] [blame] | 62 | |
Manish V Badarkhe | fcfe431 | 2022-07-12 21:48:04 +0100 | [diff] [blame] | 63 | /* DRTM error handling functions */ |
| 64 | int plat_set_drtm_error(uint64_t error_code); |
| 65 | int plat_get_drtm_error(uint64_t *error_code); |
| 66 | |
Manish V Badarkhe | b614969 | 2022-07-04 14:51:07 +0100 | [diff] [blame] | 67 | /* |
| 68 | * Platform-specific function to ensure passed region lies within |
| 69 | * Non-Secure region of DRAM |
| 70 | */ |
| 71 | int plat_drtm_validate_ns_region(uintptr_t region_start, |
| 72 | size_t region_size); |
| 73 | |
Lucian Paul-Trifu | 5ee4f4e | 2022-06-22 18:45:30 +0100 | [diff] [blame] | 74 | #endif /* PLAT_DRTM_H */ |