blob: 34af29a8ab9c687200924e5703feda161283b403 [file] [log] [blame]
XiaoDong Huang83f79a82019-06-13 10:55:50 +08001/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __CPU_ON_FIXED_ADDR_H__
8#define __CPU_ON_FIXED_ADDR_H__
9
10/*****************************************************************************
11 * define data offset in struct psram_data
12 *****************************************************************************/
13#define PSRAM_DT_SP 0x0
14#define PSRAM_DT_DDR_FUNC 0x8
15#define PSRAM_DT_DDR_DATA 0x10
16#define PSRAM_DT_DDRFLAG 0x18
17#define PSRAM_DT_MPIDR 0x1c
18#define PSRAM_DT_PM_FLAG 0x20
19#define PSRAM_DT_END 0x24
20
21/* reserve 4 byte */
22#define PSRAM_DT_END_RES4 (PSRAM_DT_END + 4)
23
24#define PSRAM_DT_SIZE_WORDS (PSRAM_DT_END_RES4 / 4)
25
26#define PM_WARM_BOOT_SHT 0
27#define PM_WARM_BOOT_BIT (1 << PM_WARM_BOOT_SHT)
28
Julius Werner53456fc2019-07-09 13:49:11 -070029#ifndef __ASSEMBLER__
XiaoDong Huang83f79a82019-06-13 10:55:50 +080030
31struct psram_data_t {
32 uint64_t sp;
33 uint64_t ddr_func;
34 uint64_t ddr_data;
35 uint32_t ddr_flag;
36 uint32_t boot_mpidr;
37 uint32_t pm_flag;
38};
39
40CASSERT(__builtin_offsetof(struct psram_data_t, sp) == PSRAM_DT_SP,
41 assert_psram_dt_sp_offset_mistmatch);
42CASSERT(__builtin_offsetof(struct psram_data_t, ddr_func) == PSRAM_DT_DDR_FUNC,
43 assert_psram_dt_ddr_func_offset_mistmatch);
44CASSERT(__builtin_offsetof(struct psram_data_t, ddr_data) == PSRAM_DT_DDR_DATA,
45 assert_psram_dt_ddr_data_offset_mistmatch);
46CASSERT(__builtin_offsetof(struct psram_data_t, ddr_flag) == PSRAM_DT_DDRFLAG,
47 assert_psram_dt_ddr_flag_offset_mistmatch);
48CASSERT(__builtin_offsetof(struct psram_data_t, boot_mpidr) == PSRAM_DT_MPIDR,
49 assert_psram_dt_mpidr_offset_mistmatch);
50
51extern void *sys_sleep_flag_sram;
52
Julius Werner53456fc2019-07-09 13:49:11 -070053#endif /* __ASSEMBLER__ */
XiaoDong Huang83f79a82019-06-13 10:55:50 +080054
55#endif