| Anson Huang | 4c28fc3 | 2018-06-05 16:12:27 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <asm_macros.S> |
| 8 | #include <platform_def.h> |
| 9 | #include <cortex_a35.h> |
| 10 | |
| 11 | .globl plat_is_my_cpu_primary |
| 12 | .globl plat_my_core_pos |
| 13 | .globl plat_calc_core_pos |
| 14 | .globl plat_reset_handler |
| 15 | .globl plat_get_my_entrypoint |
| 16 | .globl plat_secondary_cold_boot_setup |
| 17 | .globl plat_crash_console_init |
| 18 | .globl plat_crash_console_putc |
| 19 | .globl platform_mem_init |
| 20 | .globl imx_mailbox_init |
| 21 | |
| 22 | /* -------------------------------------------------------------------- |
| 23 | * Helper macro that reads the part number of the current CPU and jumps |
| 24 | * to the given label if it matches the CPU MIDR provided. |
| 25 | * |
| 26 | * Clobbers x0. |
| 27 | * -------------------------------------------------------------------- |
| 28 | */ |
| 29 | .macro jump_if_cpu_midr _cpu_midr, _label |
| 30 | |
| 31 | mrs x0, midr_el1 |
| 32 | ubfx x0, x0, MIDR_PN_SHIFT, #12 |
| 33 | cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) |
| 34 | b.eq \_label |
| 35 | |
| 36 | .endm |
| 37 | |
| 38 | /* ---------------------------------------------- |
| 39 | * The mailbox_base is used to distinguish warm/cold |
| 40 | * reset. The mailbox_base is in the data section, not |
| 41 | * in .bss, this allows function to start using this |
| 42 | * variable before the runtime memory is initialized. |
| 43 | * ---------------------------------------------- |
| 44 | */ |
| 45 | .section .data.mailbox_base |
| 46 | .align 3 |
| 47 | mailbox_base: .quad 0x0 |
| 48 | |
| 49 | /* ---------------------------------------------- |
| 50 | * unsigned int plat_is_my_cpu_primary(void); |
| 51 | * This function checks if this is the primary CPU |
| 52 | * ---------------------------------------------- |
| 53 | */ |
| 54 | func plat_is_my_cpu_primary |
| 55 | mrs x0, mpidr_el1 |
| 56 | and x0, x0, #(MPIDR_CPU_MASK) |
| 57 | cmp x0, #PLAT_PRIMARY_CPU |
| 58 | cset x0, eq |
| 59 | ret |
| 60 | endfunc plat_is_my_cpu_primary |
| 61 | |
| 62 | /* ---------------------------------------------- |
| 63 | * unsigned int plat_my_core_pos(void) |
| 64 | * This Function uses the plat_calc_core_pos() |
| 65 | * to get the index of the calling CPU. |
| 66 | * ---------------------------------------------- |
| 67 | */ |
| 68 | func plat_my_core_pos |
| 69 | mrs x0, mpidr_el1 |
| 70 | and x1, x0, #MPIDR_CPU_MASK |
| 71 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 72 | add x0, x1, x0, LSR #6 |
| 73 | ret |
| 74 | endfunc plat_my_core_pos |
| 75 | |
| 76 | /* |
| 77 | * unsigned int plat_calc_core_pos(uint64_t mpidr) |
| 78 | * helper function to calculate the core position. |
| 79 | * With this function. |
| 80 | */ |
| 81 | func plat_calc_core_pos |
| 82 | and x1, x0, #MPIDR_CPU_MASK |
| 83 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 84 | add x0, x1, x0, LSR #6 |
| 85 | ret |
| 86 | endfunc plat_calc_core_pos |
| 87 | |
| 88 | /* --------------------------------------------- |
| 89 | * function to get the entrypoint. |
| 90 | * --------------------------------------------- |
| 91 | */ |
| 92 | func plat_get_my_entrypoint |
| 93 | adrp x1, mailbox_base |
| 94 | ldr x0, [x1, :lo12:mailbox_base] |
| 95 | ret |
| 96 | endfunc plat_get_my_entrypoint |
| 97 | |
| 98 | func imx_mailbox_init |
| 99 | adrp x1, mailbox_base |
| 100 | str x0, [x1, :lo12:mailbox_base] |
| 101 | ret |
| 102 | endfunc imx_mailbox_init |
| 103 | |
| 104 | func plat_secondary_cold_boot_setup |
| 105 | b . |
| 106 | endfunc plat_secondary_cold_boot_setup |
| 107 | |
| 108 | func plat_crash_console_init |
| 109 | ret |
| 110 | endfunc plat_crash_console_init |
| 111 | |
| 112 | func plat_crash_console_putc |
| 113 | ret |
| 114 | endfunc plat_crash_console_putc |
| 115 | |
| 116 | func platform_mem_init |
| 117 | ret |
| 118 | endfunc platform_mem_init |