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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handleyed6ff952014-05-14 17:44:19 +010031#include <platform_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000035ENTRY(bl2_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
37MEMORY {
Achin Gupta4f6ad662013-10-25 09:08:21 +010038 RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
39}
40
41
42SECTIONS
43{
44 . = BL2_BASE;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000045 ASSERT(. == ALIGN(4096),
46 "BL2_BASE address is not aligned on a page boundary.")
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000048 ro . : {
49 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000050 *bl2_entrypoint.o(.text*)
51 *(.text*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000052 *(.rodata*)
Achin Guptab739f222014-01-18 16:50:09 +000053 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000054 __RO_END_UNALIGNED__ = .;
55 /*
56 * Memory page(s) mapped to this section will be marked as
57 * read-only, executable. No RW data from the next section must
58 * creep in. Ensure the rest of the current memory page is unused.
59 */
60 . = NEXT(4096);
61 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010062 } >RAM
63
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000064 .data . : {
65 __DATA_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000066 *(.data*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000067 __DATA_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010068 } >RAM
69
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000070 stacks (NOLOAD) : {
71 __STACKS_START__ = .;
72 *(tzfw_normal_stacks)
73 __STACKS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010074 } >RAM
75
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000076 /*
77 * The .bss section gets initialised to 0 at runtime.
78 * Its base address must be 16-byte aligned.
79 */
80 .bss : ALIGN(16) {
81 __BSS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000082 *(SORT_BY_ALIGNMENT(.bss*))
Achin Gupta4f6ad662013-10-25 09:08:21 +010083 *(COMMON)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000084 __BSS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010085 } >RAM
86
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000087 /*
Jeenu Viswambharan97cc9ee2014-02-24 15:20:28 +000088 * The xlat_table section is for full, aligned page tables (4K).
Achin Guptaa0cd9892014-02-09 13:30:38 +000089 * Removing them from .bss avoids forcing 4K alignment on
90 * the .bss section and eliminates the unecessary zero init
91 */
92 xlat_table (NOLOAD) : {
93 *(xlat_table)
94 } >RAM
95
96 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000097 * The base address of the coherent memory section must be page-aligned (4K)
98 * to guarantee that the coherent data are stored on their own pages and
99 * are not mixed with normal data. This is required to set up the correct
100 * memory attributes for the coherent data page tables.
101 */
102 coherent_ram (NOLOAD) : ALIGN(4096) {
103 __COHERENT_RAM_START__ = .;
104 *(tzfw_coherent_mem)
105 __COHERENT_RAM_END_UNALIGNED__ = .;
106 /*
107 * Memory page(s) mapped to this section will be marked
108 * as device memory. No other unexpected data must creep in.
109 * Ensure the rest of the current memory page is unused.
110 */
111 . = NEXT(4096);
112 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100113 } >RAM
Achin Gupta4f6ad662013-10-25 09:08:21 +0100114
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000115 __BL2_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000117 __BSS_SIZE__ = SIZEOF(.bss);
118 __COHERENT_RAM_UNALIGNED_SIZE__ =
119 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100120
121 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100122}