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Douglas Raillardd7c21b72017-06-28 15:23:03 +01001Tegra SoCs - Overview
2=====================
3
4- .. rubric:: T210
5 :name: t210
6
Dan Handley610e7e12018-03-01 18:44:00 +00007T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
8companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
9support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
10including legacy Armv7-A applications. The Cortex-A57 processors each have
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001148 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
12Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
13and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
14
15- .. rubric:: T132
16 :name: t132
17
18Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
Dan Handley610e7e12018-03-01 18:44:00 +000019fully Armv8-A architecture compatible. Each of the two Denver cores
Douglas Raillardd7c21b72017-06-28 15:23:03 +010020implements a 7-way superscalar microarchitecture (up to 7 concurrent
21micro-ops can be executed per clock), and includes a 128KB 4-way L1
22instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
23cache, which services both cores.
24
25Denver implements an innovative process called Dynamic Code Optimization,
26which optimizes frequently used software routines at runtime into dense,
27highly tuned microcode-equivalent routines. These are stored in a
28dedicated, 128MB main-memory-based optimization cache. After being read
29into the instruction cache, the optimized micro-ops are executed,
30re-fetched and executed from the instruction cache as long as needed and
31capacity allows.
32
33Effectively, this reduces the need to re-optimize the software routines.
34Instead of using hardware to extract the instruction-level parallelism
35(ILP) inherent in the code, Denver extracts the ILP once via software
36techniques, and then executes those routines repeatedly, thus amortizing
37the cost of ILP extraction over the many execution instances.
38
39Denver also features new low latency power-state transitions, in addition
40to extensive power-gating and dynamic voltage and clock scaling based on
41workloads.
42
43Directory structure
44===================
45
46- plat/nvidia/tegra/common - Common code for all Tegra SoCs
47- plat/nvidia/tegra/soc/txxx - Chip specific code
48
49Trusted OS dispatcher
50=====================
51
52Tegra supports multiple Trusted OS', Trusted Little Kernel (TLK) being one of
53them. In order to include the 'tlkd' dispatcher in the image, pass 'SPD=tlkd'
54on the command line while preparing a bl31 image. This allows other Trusted OS
55vendors to use the upstream code and include their dispatchers in the image
56without changing any makefiles.
57
58Preparing the BL31 image to run on Tegra SoCs
59=============================================
60
61.. code:: shell
62
63 CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
64 TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> bl31
65
66Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>``
67to the build command line.
68
69The Tegra platform code expects a pointer to the following platform specific
70structure via 'x1' register from the BL2 layer which is used by the
71bl31\_early\_platform\_setup() handler to extract the TZDRAM carveout base and
72size for loading the Trusted OS and the UART port ID to be used. The Tegra
73memory controller driver programs this base/size in order to restrict NS
74accesses.
75
76typedef struct plat\_params\_from\_bl2 {
77/\* TZ memory size */
78uint64\_t tzdram\_size;
79/* TZ memory base */
80uint64\_t tzdram\_base;
81/* UART port ID \*/
82int uart\_id;
83} plat\_params\_from\_bl2\_t;
84
85Power Management
86================
87
88The PSCI implementation expects each platform to expose the 'power state'
89parameter to be used during the 'SYSTEM SUSPEND' call. The state-id field
90is implementation defined on Tegra SoCs and is preferably defined by
91tegra\_def.h.
92
93Tegra configs
94=============
95
96- 'tegra\_enable\_l2\_ecc\_parity\_prot': This flag enables the L2 ECC and Parity
Dan Handley610e7e12018-03-01 18:44:00 +000097 Protection bit, for Arm Cortex-A57 CPUs, during CPU boot. This flag will
Douglas Raillardd7c21b72017-06-28 15:23:03 +010098 be enabled by Tegrs SoCs during 'Cluster power up' or 'System Suspend' exit.