| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
| 8 | #include <common/debug.h> |
| 9 | #include <lib/mmio.h> |
| 10 | #include <mce.h> |
| 11 | #include <string.h> |
| 12 | #include <tegra_def.h> |
| 13 | #include <tegra_private.h> |
| 14 | |
| 15 | #define MISCREG_CPU_RESET_VECTOR 0x2000 |
| 16 | #define MISCREG_AA64_RST_LOW 0x2004 |
| 17 | #define MISCREG_AA64_RST_HIGH 0x2008 |
| 18 | |
| 19 | #define CPU_RESET_MODE_AA64 1 |
| 20 | |
| 21 | extern void tegra_secure_entrypoint(void); |
| 22 | |
| 23 | #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM |
| 24 | extern void tegra186_cpu_reset_handler(void); |
| 25 | extern uint64_t __tegra186_smmu_ctx_start; |
| 26 | #endif |
| 27 | |
| 28 | /******************************************************************************* |
| 29 | * Setup secondary CPU vectors |
| 30 | ******************************************************************************/ |
| 31 | void plat_secondary_setup(void) |
| 32 | { |
| 33 | uint32_t addr_low, addr_high; |
| 34 | #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM |
| 35 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
| 36 | uint64_t cpu_reset_handler_base = params_from_bl2->tzdram_base; |
| 37 | #else |
| 38 | uint64_t cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint; |
| 39 | #endif |
| 40 | |
| 41 | INFO("Setting up secondary CPU boot\n"); |
| 42 | |
| 43 | #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM |
| 44 | memcpy((void *)((uintptr_t)cpu_reset_handler_base), |
| 45 | (void *)(uintptr_t)tegra186_cpu_reset_handler, |
| 46 | (uintptr_t)&__tegra186_smmu_ctx_start - |
| 47 | (uintptr_t)tegra186_cpu_reset_handler); |
| 48 | #endif |
| 49 | |
| 50 | addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; |
| 51 | addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff); |
| 52 | |
| 53 | /* write lower 32 bits first, then the upper 11 bits */ |
| 54 | mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); |
| 55 | mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); |
| 56 | |
| 57 | /* save reset vector to be used during SYSTEM_SUSPEND exit */ |
| 58 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_LO, |
| 59 | addr_low); |
| 60 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_HI, |
| 61 | addr_high); |
| 62 | |
| 63 | /* update reset vector address to the CCPLEX */ |
| 64 | mce_update_reset_vector(); |
| 65 | } |