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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7c6df5b2018-01-15 14:43:42 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#ifndef __ARM_DEF_H__
7#define __ARM_DEF_H__
8
Soby Mathewfec4eb72015-07-01 16:16:20 +01009#include <arch.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <common_def.h>
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010011#include <gic_common.h>
12#include <interrupt_props.h>
Dan Handley9df48042015-03-19 18:58:55 +000013#include <platform_def.h>
Juan Castillo9b265a82015-05-07 14:52:44 +010014#include <tbbr_img_def.h>
Scott Brandenbf404c02017-04-10 11:45:52 -070015#include <utils_def.h>
Antonio Nino Diaz719bf852017-02-23 17:22:58 +000016#include <xlat_tables_defs.h>
Dan Handley9df48042015-03-19 18:58:55 +000017
18
19/******************************************************************************
20 * Definitions common to all ARM standard platforms
21 *****************************************************************************/
22
Juan Castillo7d199412015-12-14 09:35:25 +000023/* Special value used to verify platform parameters from BL2 to BL31 */
Dan Handley9df48042015-03-19 18:58:55 +000024#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
25
Soby Mathewa869de12015-05-08 10:18:59 +010026#define ARM_SYSTEM_COUNT 1
Dan Handley9df48042015-03-19 18:58:55 +000027
28#define ARM_CACHE_WRITEBACK_SHIFT 6
29
Soby Mathewfec4eb72015-07-01 16:16:20 +010030/*
31 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
32 * power levels have a 1:1 mapping with the MPIDR affinity levels.
33 */
34#define ARM_PWR_LVL0 MPIDR_AFFLVL0
35#define ARM_PWR_LVL1 MPIDR_AFFLVL1
Soby Mathewa869de12015-05-08 10:18:59 +010036#define ARM_PWR_LVL2 MPIDR_AFFLVL2
Soby Mathewfec4eb72015-07-01 16:16:20 +010037
38/*
39 * Macros for local power states in ARM platforms encoded by State-ID field
40 * within the power-state parameter.
41 */
42/* Local power state for power domains in Run state. */
43#define ARM_LOCAL_STATE_RUN 0
44/* Local power state for retention. Valid only for CPU power domains */
45#define ARM_LOCAL_STATE_RET 1
46/* Local power state for OFF/power-down. Valid for CPU and cluster power
47 domains */
48#define ARM_LOCAL_STATE_OFF 2
49
Dan Handley9df48042015-03-19 18:58:55 +000050/* Memory location options for TSP */
51#define ARM_TRUSTED_SRAM_ID 0
52#define ARM_TRUSTED_DRAM_ID 1
53#define ARM_DRAM_ID 2
54
55/* The first 4KB of Trusted SRAM are used as shared memory */
56#define ARM_TRUSTED_SRAM_BASE 0x04000000
57#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
58#define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
59
60/* The remaining Trusted SRAM is used to load the BL images */
61#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
62 ARM_SHARED_RAM_SIZE)
63#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
64 ARM_SHARED_RAM_SIZE)
65
66/*
67 * The top 16MB of DRAM1 is configured as secure access only using the TZC
68 * - SCP TZC DRAM: If present, DRAM reserved for SCP use
69 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
70 */
David Cunado2e36de82017-01-19 10:26:16 +000071#define ARM_TZC_DRAM1_SIZE ULL(0x01000000)
Dan Handley9df48042015-03-19 18:58:55 +000072
73#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
74 ARM_DRAM1_SIZE - \
75 ARM_SCP_TZC_DRAM1_SIZE)
76#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
77#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
78 ARM_SCP_TZC_DRAM1_SIZE - 1)
79
Soby Mathew3b5156e2017-10-05 12:27:33 +010080/*
81 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime
82 * firmware. This region is meant to be NOLOAD and will not be zero
83 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be
84 * placed here.
85 */
86#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE)
87#define ARM_EL3_TZC_DRAM1_SIZE ULL(0x00200000) /* 2 MB */
88#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \
89 ARM_EL3_TZC_DRAM1_SIZE - 1)
90
Dan Handley9df48042015-03-19 18:58:55 +000091#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
92 ARM_DRAM1_SIZE - \
93 ARM_TZC_DRAM1_SIZE)
94#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
Soby Mathew3b5156e2017-10-05 12:27:33 +010095 (ARM_SCP_TZC_DRAM1_SIZE + \
96 ARM_EL3_TZC_DRAM1_SIZE))
Dan Handley9df48042015-03-19 18:58:55 +000097#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
98 ARM_AP_TZC_DRAM1_SIZE - 1)
99
Soby Mathew7e4d6652017-05-10 11:50:30 +0100100/* Define the Access permissions for Secure peripherals to NS_DRAM */
101#if ARM_CRYPTOCELL_INTEG
102/*
103 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
104 * This is required by CryptoCell to authenticate BL33 which is loaded
105 * into the Non Secure DDR.
106 */
107#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD
108#else
109#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE
110#endif
111
Summer Qin9db8f2e2017-04-24 16:49:28 +0100112#ifdef SPD_opteed
113/*
Jens Wiklanderae73b162017-08-24 15:39:09 +0200114 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
115 * load/authenticate the trusted os extra image. The first 512KB of
116 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
117 * for OPTEE is paged image which only include the paging part using
118 * virtual memory but without "init" data. OPTEE will copy the "init" data
119 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
120 * extra image behind the "init" data.
Summer Qin9db8f2e2017-04-24 16:49:28 +0100121 */
Jens Wiklanderae73b162017-08-24 15:39:09 +0200122#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \
123 ARM_AP_TZC_DRAM1_SIZE - \
124 ARM_OPTEE_PAGEABLE_LOAD_SIZE)
125#define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x400000
Summer Qin9db8f2e2017-04-24 16:49:28 +0100126#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
127 ARM_OPTEE_PAGEABLE_LOAD_BASE, \
128 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \
129 MT_MEMORY | MT_RW | MT_SECURE)
Soby Mathew874fc9e2017-09-01 13:43:50 +0100130
131/*
132 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging
133 * support is enabled).
134 */
135#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
136 BL32_BASE, \
137 BL32_LIMIT - BL32_BASE, \
138 MT_MEMORY | MT_RW | MT_SECURE)
Summer Qin9db8f2e2017-04-24 16:49:28 +0100139#endif /* SPD_opteed */
Dan Handley9df48042015-03-19 18:58:55 +0000140
141#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
142#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
143 ARM_TZC_DRAM1_SIZE)
144#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
145 ARM_NS_DRAM1_SIZE - 1)
146
David Cunado2e36de82017-01-19 10:26:16 +0000147#define ARM_DRAM1_BASE ULL(0x80000000)
148#define ARM_DRAM1_SIZE ULL(0x80000000)
Dan Handley9df48042015-03-19 18:58:55 +0000149#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
150 ARM_DRAM1_SIZE - 1)
151
David Cunado2e36de82017-01-19 10:26:16 +0000152#define ARM_DRAM2_BASE ULL(0x880000000)
Dan Handley9df48042015-03-19 18:58:55 +0000153#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
154#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
155 ARM_DRAM2_SIZE - 1)
156
157#define ARM_IRQ_SEC_PHY_TIMER 29
158
159#define ARM_IRQ_SEC_SGI_0 8
160#define ARM_IRQ_SEC_SGI_1 9
161#define ARM_IRQ_SEC_SGI_2 10
162#define ARM_IRQ_SEC_SGI_3 11
163#define ARM_IRQ_SEC_SGI_4 12
164#define ARM_IRQ_SEC_SGI_5 13
165#define ARM_IRQ_SEC_SGI_6 14
166#define ARM_IRQ_SEC_SGI_7 15
167
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000168/*
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100169 * List of secure interrupts are deprecated, but are retained only to support
170 * legacy configurations.
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000171 */
172#define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \
173 ARM_IRQ_SEC_SGI_1, \
174 ARM_IRQ_SEC_SGI_2, \
175 ARM_IRQ_SEC_SGI_3, \
176 ARM_IRQ_SEC_SGI_4, \
177 ARM_IRQ_SEC_SGI_5, \
178 ARM_IRQ_SEC_SGI_7
179
180#define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \
181 ARM_IRQ_SEC_SGI_6
182
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100183/*
184 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
185 * terminology. On a GICv2 system or mode, the lists will be merged and treated
186 * as Group 0 interrupts.
187 */
188#define ARM_G1S_IRQ_PROPS(grp) \
189 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
190 GIC_INTR_CFG_LEVEL), \
191 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
192 GIC_INTR_CFG_EDGE), \
193 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
194 GIC_INTR_CFG_EDGE), \
195 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
196 GIC_INTR_CFG_EDGE), \
197 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
198 GIC_INTR_CFG_EDGE), \
199 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
200 GIC_INTR_CFG_EDGE), \
201 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
202 GIC_INTR_CFG_EDGE)
203
204#define ARM_G0_IRQ_PROPS(grp) \
Jeenu Viswambharana5acc0a2017-09-22 08:32:10 +0100205 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100206 GIC_INTR_CFG_EDGE), \
207 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
208 GIC_INTR_CFG_EDGE)
209
Dan Handley9df48042015-03-19 18:58:55 +0000210#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
211 ARM_SHARED_RAM_BASE, \
212 ARM_SHARED_RAM_SIZE, \
Juan Castillo2e86cb12016-01-13 15:01:09 +0000213 MT_DEVICE | MT_RW | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +0000214
215#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
216 ARM_NS_DRAM1_BASE, \
217 ARM_NS_DRAM1_SIZE, \
218 MT_MEMORY | MT_RW | MT_NS)
219
Roberto Vargasf8fda102017-08-08 11:27:20 +0100220#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \
221 ARM_DRAM2_BASE, \
222 ARM_DRAM2_SIZE, \
223 MT_MEMORY | MT_RW | MT_NS)
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +0100224#ifdef SPD_tspd
Roberto Vargasf8fda102017-08-08 11:27:20 +0100225
Dan Handley9df48042015-03-19 18:58:55 +0000226#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
227 TSP_SEC_MEM_BASE, \
228 TSP_SEC_MEM_SIZE, \
229 MT_MEMORY | MT_RW | MT_SECURE)
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +0100230#endif
Dan Handley9df48042015-03-19 18:58:55 +0000231
David Wang0ba499f2016-03-07 11:02:57 +0800232#if ARM_BL31_IN_DRAM
233#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
234 BL31_BASE, \
235 PLAT_ARM_MAX_BL31_SIZE, \
236 MT_MEMORY | MT_RW | MT_SECURE)
237#endif
Dan Handley9df48042015-03-19 18:58:55 +0000238
Soby Mathew3b5156e2017-10-05 12:27:33 +0100239#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \
240 ARM_EL3_TZC_DRAM1_BASE, \
241 ARM_EL3_TZC_DRAM1_SIZE, \
242 MT_MEMORY | MT_RW | MT_SECURE)
243
Dan Handley9df48042015-03-19 18:58:55 +0000244/*
245 * The number of regions like RO(code), coherent and data required by
246 * different BL stages which need to be mapped in the MMU.
247 */
Sandrine Bailleux4c8138a2018-06-06 16:35:40 +0200248#if USE_COHERENT_MEM
Chris Kay24690322018-05-09 15:14:06 +0100249# define ARM_BL_REGIONS 4
Dan Handley9df48042015-03-19 18:58:55 +0000250#else
Chris Kay24690322018-05-09 15:14:06 +0100251# define ARM_BL_REGIONS 3
Dan Handley9df48042015-03-19 18:58:55 +0000252#endif
253
254#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
255 ARM_BL_REGIONS)
256
257/* Memory mapped Generic timer interfaces */
258#define ARM_SYS_CNTCTL_BASE 0x2a430000
259#define ARM_SYS_CNTREAD_BASE 0x2a800000
260#define ARM_SYS_TIMCTL_BASE 0x2a810000
Soby Mathew2d9f7952018-06-11 16:21:30 +0100261#define ARM_SYS_CNT_BASE_S 0x2a820000
262#define ARM_SYS_CNT_BASE_NS 0x2a830000
Dan Handley9df48042015-03-19 18:58:55 +0000263
264#define ARM_CONSOLE_BAUDRATE 115200
265
Juan Castillob6132f12015-10-06 14:01:35 +0100266/* Trusted Watchdog constants */
267#define ARM_SP805_TWDG_BASE 0x2a490000
268#define ARM_SP805_TWDG_CLK_HZ 32768
269/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
270 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
271#define ARM_TWDG_TIMEOUT_SEC 128
272#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
273 ARM_TWDG_TIMEOUT_SEC)
274
Dan Handley9df48042015-03-19 18:58:55 +0000275/******************************************************************************
276 * Required platform porting definitions common to all ARM standard platforms
277 *****************************************************************************/
278
Roberto Vargasf8fda102017-08-08 11:27:20 +0100279/*
280 * We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for
281 * AArch64 builds
282 */
283#ifdef AARCH64
David Cunadoc1503122018-02-16 21:12:58 +0000284#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
285#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
Roberto Vargasf8fda102017-08-08 11:27:20 +0100286#else
David Cunadoc1503122018-02-16 21:12:58 +0000287#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
288#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
Roberto Vargasf8fda102017-08-08 11:27:20 +0100289#endif
290
Dan Handley9df48042015-03-19 18:58:55 +0000291
Soby Mathewfec4eb72015-07-01 16:16:20 +0100292/*
293 * This macro defines the deepest retention state possible. A higher state
294 * id will represent an invalid or a power down state.
295 */
296#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
297
298/*
299 * This macro defines the deepest power down states possible. Any state ID
300 * higher than this is invalid.
301 */
302#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
303
Dan Handley9df48042015-03-19 18:58:55 +0000304/*
305 * Some data must be aligned on the biggest cache line size in the platform.
306 * This is known only to the platform as it might have a combination of
307 * integrated and external caches.
308 */
309#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
310
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000311/*
312 * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
313 * and limit. Leave enough space of BL2 meminfo.
314 */
315#define ARM_TB_FW_CONFIG_BASE ARM_BL_RAM_BASE + sizeof(meminfo_t)
Soby Mathewaf14b462018-06-01 16:53:38 +0100316#define ARM_TB_FW_CONFIG_LIMIT ARM_BL_RAM_BASE + PAGE_SIZE
Dan Handley9df48042015-03-19 18:58:55 +0000317
318/*******************************************************************************
319 * BL1 specific defines.
320 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
321 * addresses.
322 ******************************************************************************/
323#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
324#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
325 + PLAT_ARM_TRUSTED_ROM_SIZE)
326/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000327 * Put BL1 RW at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000328 */
Dan Handley9df48042015-03-19 18:58:55 +0000329#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
330 ARM_BL_RAM_SIZE - \
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000331 PLAT_ARM_MAX_BL1_RW_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000332#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
333
334/*******************************************************************************
335 * BL2 specific defines.
336 ******************************************************************************/
Soby Mathewaf14b462018-06-01 16:53:38 +0100337#if BL2_AT_EL3
Dimitris Papastamos25836492018-06-11 11:07:58 +0100338/* Put BL2 towards the middle of the Trusted SRAM */
Soby Mathewaf14b462018-06-01 16:53:38 +0100339#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
Dimitris Papastamos25836492018-06-11 11:07:58 +0100340 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000)
Roberto Vargas52207802017-11-17 13:22:18 +0000341#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
342
David Wang0ba499f2016-03-07 11:02:57 +0800343#else
Dan Handley9df48042015-03-19 18:58:55 +0000344/*
Soby Mathewaf14b462018-06-01 16:53:38 +0100345 * Put BL2 just below BL1.
Dan Handley9df48042015-03-19 18:58:55 +0000346 */
Soby Mathewaf14b462018-06-01 16:53:38 +0100347#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
348#define BL2_LIMIT BL1_RW_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800349#endif
Dan Handley9df48042015-03-19 18:58:55 +0000350
351/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000352 * BL31 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000353 ******************************************************************************/
David Wang0ba499f2016-03-07 11:02:57 +0800354#if ARM_BL31_IN_DRAM
355/*
356 * Put BL31 at the bottom of TZC secured DRAM
357 */
358#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
359#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
360 PLAT_ARM_MAX_BL31_SIZE)
Qixiang Xua5f72812017-08-31 11:45:32 +0800361#elif (RESET_TO_BL31)
362/*
363 * Put BL31_BASE in the middle of the Trusted SRAM.
364 */
365#define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \
366 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1))
367#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
David Wang0ba499f2016-03-07 11:02:57 +0800368#else
Soby Mathewaf14b462018-06-01 16:53:38 +0100369/* Put BL31 below BL2 in the Trusted SRAM.*/
370#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
371 - PLAT_ARM_MAX_BL31_SIZE)
372#define BL31_PROGBITS_LIMIT BL2_BASE
Dimitris Papastamos25836492018-06-11 11:07:58 +0100373/*
374 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is
375 * because in the BL2_AT_EL3 configuration, BL2 is always resident.
376 */
377#if BL2_AT_EL3
378#define BL31_LIMIT BL2_BASE
379#else
Dan Handley9df48042015-03-19 18:58:55 +0000380#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
David Wang0ba499f2016-03-07 11:02:57 +0800381#endif
Dimitris Papastamos25836492018-06-11 11:07:58 +0100382#endif
Dan Handley9df48042015-03-19 18:58:55 +0000383
Soby Mathewbf169232017-11-14 14:10:10 +0000384#if defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME
Dan Handley9df48042015-03-19 18:58:55 +0000385/*******************************************************************************
Soby Mathewbf169232017-11-14 14:10:10 +0000386 * BL32 specific defines for EL3 runtime in AArch32 mode
387 ******************************************************************************/
388# if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
Soby Mathewaf14b462018-06-01 16:53:38 +0100389/*
390 * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding
391 * the page reserved for fw_configs) to BL32
392 */
393# define BL32_BASE ARM_TB_FW_CONFIG_LIMIT
Soby Mathewbf169232017-11-14 14:10:10 +0000394# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
395# else
Soby Mathewaf14b462018-06-01 16:53:38 +0100396/* Put BL32 below BL2 in the Trusted SRAM.*/
397# define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
398 - PLAT_ARM_MAX_BL32_SIZE)
399# define BL32_PROGBITS_LIMIT BL2_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000400# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
401# endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */
402
403#else
404/*******************************************************************************
405 * BL32 specific defines for EL3 runtime in AArch64 mode
Dan Handley9df48042015-03-19 18:58:55 +0000406 ******************************************************************************/
407/*
408 * On ARM standard platforms, the TSP can execute from Trusted SRAM,
409 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
410 * controller.
411 */
Soby Mathewbf169232017-11-14 14:10:10 +0000412# if ENABLE_SPM
413# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
414# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
415# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
416# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000417 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000418# elif ARM_BL31_IN_DRAM
419# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800420 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000421# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \
David Wang0ba499f2016-03-07 11:02:57 +0800422 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000423# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800424 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000425# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800426 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000427# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
428# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
429# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
Soby Mathewaf14b462018-06-01 16:53:38 +0100430# define TSP_PROGBITS_LIMIT BL31_BASE
431# define BL32_BASE ARM_TB_FW_CONFIG_LIMIT
Soby Mathewbf169232017-11-14 14:10:10 +0000432# define BL32_LIMIT BL31_BASE
433# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
434# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
435# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
436# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
437# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
Dan Handley9df48042015-03-19 18:58:55 +0000438 + (1 << 21))
Soby Mathewbf169232017-11-14 14:10:10 +0000439# elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
440# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
441# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
442# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
443# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
Dan Handley9df48042015-03-19 18:58:55 +0000444 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000445# else
446# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
447# endif
448#endif /* AARCH32 || JUNO_AARCH32_EL3_RUNTIME */
Dan Handley9df48042015-03-19 18:58:55 +0000449
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000450/*
451 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no
452 * SPD and no SPM, as they are the only ones that can be used as BL32.
453 */
Soby Mathewbf169232017-11-14 14:10:10 +0000454#if !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME)
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000455# if defined(SPD_none) && !ENABLE_SPM
456# undef BL32_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000457# endif /* defined(SPD_none) && !ENABLE_SPM */
458#endif /* !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) */
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100459
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100460/*******************************************************************************
461 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
462 ******************************************************************************/
463#define BL2U_BASE BL2_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000464#define BL2U_LIMIT BL2_LIMIT
465
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100466#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
Yatharth Kocharf11b29a2016-02-01 11:04:46 +0000467#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000)
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100468
Dan Handley9df48042015-03-19 18:58:55 +0000469/*
470 * ID of the secure physical generic timer interrupt used by the TSP.
471 */
472#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
473
474
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100475/*
476 * One cache line needed for bakery locks on ARM platforms
477 */
478#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
479
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100480/* Priority levels for ARM platforms */
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +0000481#define PLAT_RAS_PRI 0x10
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100482#define PLAT_SDEI_CRITICAL_PRI 0x60
483#define PLAT_SDEI_NORMAL_PRI 0x70
484
485/* ARM platforms use 3 upper bits of secure interrupt priority */
486#define ARM_PRI_BITS 3
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100487
Jeenu Viswambharana5acc0a2017-09-22 08:32:10 +0100488/* SGI used for SDEI signalling */
489#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0
490
491/* ARM SDEI dynamic private event numbers */
492#define ARM_SDEI_DP_EVENT_0 1000
493#define ARM_SDEI_DP_EVENT_1 1001
494#define ARM_SDEI_DP_EVENT_2 1002
495
496/* ARM SDEI dynamic shared event numbers */
497#define ARM_SDEI_DS_EVENT_0 2000
498#define ARM_SDEI_DS_EVENT_1 2001
499#define ARM_SDEI_DS_EVENT_2 2002
500
Jeenu Viswambharan6e284462017-12-08 10:38:24 +0000501#define ARM_SDEI_PRIVATE_EVENTS \
502 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
503 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
504 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
505 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
506
507#define ARM_SDEI_SHARED_EVENTS \
508 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
509 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
510 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
511
Dan Handley9df48042015-03-19 18:58:55 +0000512#endif /* __ARM_DEF_H__ */