| Pankaj Gupta | b9508bf | 2020-12-09 14:02:39 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2021 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef PLAT_GICV2_H |
| 9 | #define PLAT_GICV2_H |
| 10 | |
| 11 | #include <drivers/arm/gicv2.h> |
| 12 | |
| 13 | /* register offsets */ |
| 14 | #define GICD_CTLR_OFFSET 0x0 |
| 15 | #define GICD_CPENDSGIR3_OFFSET 0xF1C |
| 16 | #define GICD_SPENDSGIR3_OFFSET 0xF2C |
| 17 | #define GICD_SGIR_OFFSET 0xF00 |
| 18 | #define GICD_IGROUPR0_OFFSET 0x080 |
| 19 | #define GICD_TYPER_OFFSET 0x0004 |
| 20 | #define GICD_ISENABLER0_OFFSET 0x0100 |
| 21 | #define GICD_ICENABLER0_OFFSET 0x0180 |
| 22 | #define GICD_IPRIORITYR3_OFFSET 0x040C |
| 23 | #define GICD_ISENABLERn_OFFSET 0x0100 |
| 24 | #define GICD_ISACTIVER0_OFFSET 0x300 |
| 25 | |
| 26 | #define GICC_CTLR_OFFSET 0x0 |
| 27 | #define GICC_PMR_OFFSET 0x0004 |
| 28 | #define GICC_IAR_OFFSET 0x000C |
| 29 | #define GICC_DIR_OFFSET 0x1000 |
| 30 | #define GICC_EOIR_OFFSET 0x0010 |
| 31 | |
| 32 | /* bitfield masks */ |
| 33 | #define GICC_CTLR_EN_GRP0 0x1 |
| 34 | #define GICC_CTLR_EN_GRP1 0x2 |
| 35 | #define GICC_CTLR_EOImodeS_MASK 0x200 |
| 36 | #define GICC_CTLR_DIS_BYPASS 0x60 |
| 37 | #define GICC_CTLR_CBPR_MASK 0x10 |
| 38 | #define GICC_CTLR_FIQ_EN_MASK 0x8 |
| 39 | #define GICC_CTLR_ACKCTL_MASK 0x4 |
| 40 | #define GICC_PMR_FILTER 0xFF |
| 41 | |
| 42 | #define GICD_CTLR_EN_GRP0 0x1 |
| 43 | #define GICD_CTLR_EN_GRP1 0x2 |
| 44 | #define GICD_IGROUP0_SGI15 0x8000 |
| 45 | #define GICD_ISENABLE0_SGI15 0x8000 |
| 46 | #define GICD_ICENABLE0_SGI15 0x8000 |
| 47 | #define GICD_ISACTIVER0_SGI15 0x8000 |
| 48 | #define GICD_CPENDSGIR_CLR_MASK 0xFF000000 |
| 49 | #define GICD_IPRIORITY_SGI15_MASK 0xFF000000 |
| 50 | #define GICD_SPENDSGIR3_SGI15_MASK 0xFF000000 |
| 51 | #define GICD_SPENDSGIR3_SGI15_OFFSET 0x18 |
| 52 | |
| 53 | #ifndef __ASSEMBLER__ |
| 54 | |
| 55 | /* GIC common API's */ |
| 56 | void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr, |
| 57 | const uintptr_t nxp_gicc_addr, |
| 58 | uint8_t plat_core_count, |
| 59 | interrupt_prop_t *ls_interrupt_props, |
| 60 | uint8_t ls_interrupt_prop_count, |
| 61 | uint32_t *target_mask_array); |
| 62 | void plat_ls_gic_init(void); |
| 63 | void plat_ls_gic_cpuif_enable(void); |
| 64 | void plat_ls_gic_cpuif_disable(void); |
| 65 | void plat_ls_gic_redistif_on(void); |
| 66 | void plat_ls_gic_redistif_off(void); |
| 67 | void plat_gic_pcpu_init(void); |
| 68 | /* GIC utility functions */ |
| 69 | void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base); |
| 70 | #endif |
| 71 | |
| 72 | #endif /* PLAT_GICV2_H */ |