Paul Beesley | ea22512 | 2019-02-11 17:54:45 +0000 | [diff] [blame^] | 1 | Trusted Firmware-A - version 2.1 |
| 2 | ================================ |
| 3 | |
| 4 | .. section-numbering:: |
| 5 | :suffix: . |
| 6 | |
| 7 | .. contents:: |
| 8 | |
| 9 | Trusted Firmware-A (TF-A) provides a reference implementation of secure world |
| 10 | software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing |
| 11 | at Exception Level 3 (EL3). It implements various Arm interface standards, |
| 12 | such as: |
| 13 | |
| 14 | - The `Power State Coordination Interface (PSCI)`_ |
| 15 | - `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)`_ |
| 16 | - `SMC Calling Convention`_ |
| 17 | - `System Control and Management Interface (SCMI)`_ |
| 18 | - `Software Delegated Exception Interface (SDEI)`_ |
| 19 | |
| 20 | Where possible, the code is designed for reuse or porting to other Armv7-A and |
| 21 | Armv8-A model and hardware platforms. |
| 22 | |
| 23 | This release provides a suitable starting point for productization of secure |
| 24 | world boot and runtime firmware, in either the AArch32 or AArch64 execution |
| 25 | states. |
| 26 | |
| 27 | Users are encouraged to do their own security validation, including penetration |
| 28 | testing, on any secure world code derived from TF-A. |
| 29 | |
| 30 | Arm will continue development in collaboration with interested parties to |
| 31 | provide a full reference implementation of Secure Monitor code and Arm standards |
| 32 | to the benefit of all developers working with Armv7-A and Armv8-A TrustZone |
| 33 | technology. |
| 34 | |
| 35 | Documentation contents |
| 36 | ---------------------- |
| 37 | |
| 38 | The `Trusted Firmware-A Documentation Contents`_ page contains an overview of |
| 39 | the documentation that is available, with links to facilitate easier browsing. |
| 40 | |
| 41 | License |
| 42 | ------- |
| 43 | |
| 44 | The software is provided under a BSD-3-Clause `license`_. Contributions to this |
| 45 | project are accepted under the same license with developer sign-off as |
| 46 | described in the `Contributing Guidelines`_. |
| 47 | |
| 48 | This project contains code from other projects as listed below. The original |
| 49 | license text is included in those source files. |
| 50 | |
| 51 | - The libc source code is derived from `FreeBSD`_ and `SCC`_. FreeBSD uses |
| 52 | various BSD licenses, including BSD-3-Clause and BSD-2-Clause. The SCC code |
| 53 | is used under the BSD-3-Clause license with the author's permission. |
| 54 | |
| 55 | - The libfdt source code is disjunctively dual licensed |
| 56 | (GPL-2.0+ OR BSD-2-Clause). It is used by this project under the terms of |
| 57 | the BSD-2-Clause license. Any contributions to this code must be made under |
| 58 | the terms of both licenses. |
| 59 | |
| 60 | - The LLVM compiler-rt source code is disjunctively dual licensed |
| 61 | (NCSA OR MIT). It is used by this project under the terms of the NCSA |
| 62 | license (also known as the University of Illinois/NCSA Open Source License), |
| 63 | which is a permissive license compatible with BSD-3-Clause. Any |
| 64 | contributions to this code must be made under the terms of both licenses. |
| 65 | |
| 66 | - The zlib source code is licensed under the Zlib license, which is a |
| 67 | permissive license compatible with BSD-3-Clause. |
| 68 | |
| 69 | - Some STMicroelectronics platform source code is disjunctively dual licensed |
| 70 | (GPL-2.0+ OR BSD-3-Clause). It is used by this project under the terms of the |
| 71 | BSD-3-Clause license. Any contributions to this code must be made under the |
| 72 | terms of both licenses. |
| 73 | |
| 74 | Functionality |
| 75 | ------------- |
| 76 | |
| 77 | - Initialization of the secure world, for example exception vectors, control |
| 78 | registers and interrupts for the platform. |
| 79 | |
| 80 | - Library support for CPU specific reset and power down sequences. This |
| 81 | includes support for errata workarounds and the latest Arm DynamIQ CPUs. |
| 82 | |
| 83 | - Drivers to enable standard initialization of Arm System IP, for example |
| 84 | Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI), |
| 85 | Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone |
| 86 | Controller (TZC). |
| 87 | |
| 88 | - A generic `SCMI`_ driver to interface with conforming power controllers, for |
| 89 | example the Arm System Control Processor (SCP). |
| 90 | |
| 91 | - SMC (Secure Monitor Call) handling, conforming to the `SMC Calling |
| 92 | Convention`_ using an EL3 runtime services framework. |
| 93 | |
| 94 | - `PSCI`_ library support for CPU, cluster and system power management |
| 95 | use-cases. |
| 96 | This library is pre-integrated with the AArch64 EL3 Runtime Software, and |
| 97 | is also suitable for integration with other AArch32 EL3 Runtime Software, |
| 98 | for example an AArch32 Secure OS. |
| 99 | |
| 100 | - A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate `PSCI`_ library |
| 101 | integration with AArch32 EL3 Runtime Software. |
| 102 | |
| 103 | - Secure Monitor library code such as world switching, EL1 context management |
| 104 | and interrupt routing. |
| 105 | When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the |
| 106 | AArch64 EL3 Runtime Software must be integrated with a Secure Payload |
| 107 | Dispatcher (SPD) component to customize the interaction with the SP. |
| 108 | |
| 109 | - A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP |
| 110 | interaction with PSCI. |
| 111 | |
| 112 | - SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_ |
| 113 | and `Trusty Secure OS`_. |
| 114 | |
| 115 | - A Trusted Board Boot implementation, conforming to all mandatory TBBR |
| 116 | requirements. This includes image authentication, Firmware Update (or |
| 117 | recovery mode), and packaging of the various firmware images into a |
| 118 | Firmware Image Package (FIP). |
| 119 | |
| 120 | - Pre-integration of TBB with the Arm CryptoCell product, to take advantage of |
| 121 | its hardware Root of Trust and crypto acceleration services. |
| 122 | |
| 123 | - Reliability, Availability, and Serviceability (RAS) functionality, including |
| 124 | |
| 125 | - A Secure Partition Manager (SPM) to manage Secure Partitions in |
| 126 | Secure-EL0, which can be used to implement simple management and |
| 127 | security services. |
| 128 | |
| 129 | - An SDEI dispatcher to route interrupt-based SDEI events. |
| 130 | |
| 131 | - An Exception Handling Framework (EHF) that allows dispatching of EL3 |
| 132 | interrupts to their registered handlers, to facilitate firmware-first |
| 133 | error handling. |
| 134 | |
| 135 | - A dynamic configuration framework that enables each of the firmware images |
| 136 | to be configured at runtime if required by the platform. It also enables |
| 137 | loading of a hardware configuration (for example, a kernel device tree) |
| 138 | as part of the FIP, to be passed through the firmware stages. |
| 139 | |
| 140 | - Support for alternative boot flows, for example to support platforms where |
| 141 | the EL3 Runtime Software is loaded using other firmware or a separate |
| 142 | secure system processor, or where a non-TF-A ROM expects BL2 to be loaded |
| 143 | at EL3. |
| 144 | |
| 145 | - Support for the GCC, LLVM and Arm Compiler 6 toolchains. |
| 146 | |
| 147 | - Support for combining several libraries into a "romlib" image that may be |
| 148 | shared across images to reduce memory footprint. The romlib image is stored |
| 149 | in ROM but is accessed through a jump-table that may be stored |
| 150 | in read-write memory, allowing for the library code to be patched. |
| 151 | |
| 152 | - A prototype implementation of a Secure Partition Manager (SPM) that is based |
| 153 | on the SPCI Alpha 1 and SPRT draft specifications. |
| 154 | |
| 155 | - Support for ARMv8.3 pointer authentication in the normal and secure worlds. |
| 156 | The use of pointer authentication in the normal world is enabled whenever |
| 157 | architectural support is available, without the need for additional build |
| 158 | flags. Use of pointer authentication in the secure world remains an |
| 159 | experimental configuration at this time and requires the ``ENABLE_PAUTH`` |
| 160 | build flag to be set. |
| 161 | |
| 162 | - Position-Independent Executable (PIE) support. Initially for BL31 only, with |
| 163 | further support to be added in a future release. |
| 164 | |
| 165 | For a full description of functionality and implementation details, please |
| 166 | see the `Firmware Design`_ and supporting documentation. The `Change Log`_ |
| 167 | provides details of changes made since the last release. |
| 168 | |
| 169 | Platforms |
| 170 | --------- |
| 171 | |
| 172 | Various AArch32 and AArch64 builds of this release have been tested on r0, r1 |
| 173 | and r2 variants of the `Juno Arm Development Platform`_. |
| 174 | |
| 175 | The latest version of the AArch64 build of TF-A has been tested on the following |
| 176 | Arm FVPs without shifted affinities, and that do not support threaded CPU cores |
| 177 | (64-bit host machine only). |
| 178 | |
| 179 | The FVP models used are Version 11.5 Build 33, unless otherwise stated. |
| 180 | |
| 181 | - ``FVP_Base_AEMv8A-AEMv8A`` |
| 182 | - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` |
| 183 | - ``FVP_Base_RevC-2xAEMv8A`` |
| 184 | - ``FVP_Base_Cortex-A32x4`` |
| 185 | - ``FVP_Base_Cortex-A35x4`` |
| 186 | - ``FVP_Base_Cortex-A53x4`` |
| 187 | - ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` |
| 188 | - ``FVP_Base_Cortex-A55x4`` |
| 189 | - ``FVP_Base_Cortex-A57x1-A53x1`` |
| 190 | - ``FVP_Base_Cortex-A57x2-A53x4`` |
| 191 | - ``FVP_Base_Cortex-A57x4-A53x4`` |
| 192 | - ``FVP_Base_Cortex-A57x4`` |
| 193 | - ``FVP_Base_Cortex-A72x4-A53x4`` |
| 194 | - ``FVP_Base_Cortex-A72x4`` |
| 195 | - ``FVP_Base_Cortex-A73x4-A53x4`` |
| 196 | - ``FVP_Base_Cortex-A73x4`` |
| 197 | - ``FVP_Base_Cortex-A75x4`` |
| 198 | - ``FVP_Base_Cortex-A76x4`` |
| 199 | - ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model) |
| 200 | - ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model) |
| 201 | - ``FVP_Base_Neoverse-N1x4`` (Tested with internal model) |
| 202 | - ``FVP_Base_Deimos`` |
| 203 | - ``FVP_CSS_SGI-575`` (Version 11.3 build 42) |
| 204 | - ``FVP_CSS_SGM-775`` (Version 11.3 build 42) |
| 205 | - ``FVP_RD_E1Edge`` (Version 11.3 build 42) |
| 206 | - ``FVP_RD_N1Edge`` (Version 11.3 build 42) |
| 207 | - ``Foundation_Platform`` |
| 208 | |
| 209 | The latest version of the AArch32 build of TF-A has been tested on the following |
| 210 | Arm FVPs without shifted affinities, and that do not support threaded CPU cores |
| 211 | (64-bit host machine only). |
| 212 | |
| 213 | - ``FVP_Base_AEMv8A-AEMv8A`` |
| 214 | - ``FVP_Base_Cortex-A32x4`` |
| 215 | |
| 216 | NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities. |
| 217 | |
| 218 | The Foundation FVP can be downloaded free of charge. The Base FVPs can be |
| 219 | licensed from Arm. See the `Arm FVP website`_. |
| 220 | |
| 221 | All the above platforms have been tested with `Linaro Release 18.04`_. |
| 222 | |
| 223 | This release also contains the following platform support: |
| 224 | |
| 225 | - Allwinner sun50i_a64 and sun50i_h6 |
| 226 | - Amlogic Meson S905 (GXBB) |
| 227 | - Amlogic Meson S905x (GXL) |
| 228 | - Arm Juno Software Development Platform |
| 229 | - Arm Neoverse N1 System Development Platform (N1SDP) |
| 230 | - Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP |
| 231 | - Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP |
| 232 | - Arm SGI-575 and SGM-775 |
| 233 | - Arm Versatile Express FVP |
| 234 | - HiKey, HiKey960 and Poplar boards |
| 235 | - Intel Stratix 10 SoC FPGA |
| 236 | - Marvell Armada 3700 and 8K |
| 237 | - MediaTek MT6795 and MT8173 SoCs |
| 238 | - NVIDIA T132, T186 and T210 SoCs |
| 239 | - NXP QorIQ LS1043A, i.MX8MM, i.MX8MQ, i.MX8QX, i.MX8QM and i.MX7Solo WaRP7 |
| 240 | - QEMU |
| 241 | - Raspberry Pi 3 |
| 242 | - Renesas R-Car Generation 3 |
| 243 | - RockChip RK3328, RK3368 and RK3399 SoCs |
| 244 | - Socionext UniPhier SoC family and SynQuacer SC2A11 SoCs |
| 245 | - STMicroelectronics STM32MP1 |
| 246 | - Texas Instruments K3 SoCs |
| 247 | - Xilinx Versal and Zynq UltraScale + MPSoC |
| 248 | |
| 249 | Still to come |
| 250 | ------------- |
| 251 | |
| 252 | - Support for additional platforms. |
| 253 | |
| 254 | - Refinements to Position Independent Executable (PIE) support. |
| 255 | |
| 256 | - Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT |
| 257 | specifications continue to evolve. |
| 258 | |
| 259 | - Documentation enhancements. |
| 260 | |
| 261 | - Ongoing support for new architectural features, CPUs and System IP. |
| 262 | |
| 263 | - Ongoing support for new Arm system architecture specifications. |
| 264 | |
| 265 | - Ongoing security hardening, optimization and quality improvements. |
| 266 | |
| 267 | For a full list of detailed issues in the current code, please see the `Change |
| 268 | Log`_ and the `issue tracker`_. |
| 269 | |
| 270 | Getting started |
| 271 | --------------- |
| 272 | |
| 273 | See the `User Guide`_ for instructions on how to download, install, build and |
| 274 | use TF-A with the Arm `FVP`_\ s. |
| 275 | |
| 276 | See the `Firmware Design`_ for information on how TF-A works. |
| 277 | |
| 278 | See the `Porting Guide`_ as well for information about how to use this |
| 279 | software on another Armv7-A or Armv8-A platform. |
| 280 | |
| 281 | See the `Contributing Guidelines`_ for information on how to contribute to this |
| 282 | project and the `Acknowledgments`_ file for a list of contributors to the |
| 283 | project. |
| 284 | |
| 285 | IRC channel |
| 286 | ~~~~~~~~~~~ |
| 287 | |
| 288 | Development discussion takes place on the #trusted-firmware-a channel |
| 289 | on the Freenode IRC network. This is not an official support channel. |
| 290 | If you have an issue to raise, please use the `issue tracker`_. |
| 291 | |
| 292 | Feedback and support |
| 293 | ~~~~~~~~~~~~~~~~~~~~ |
| 294 | |
| 295 | Arm welcomes any feedback on TF-A. If you think you have found a security |
| 296 | vulnerability, please report this using the process defined in the TF-A |
| 297 | `Security Center`_. For all other feedback, please use the |
| 298 | `issue tracker`_. |
| 299 | |
| 300 | Arm licensees may contact Arm directly via their partner managers. |
| 301 | |
| 302 | Security advisories |
| 303 | ------------------- |
| 304 | |
| 305 | - `Security Advisory TFV-1`_ |
| 306 | - `Security Advisory TFV-2`_ |
| 307 | - `Security Advisory TFV-3`_ |
| 308 | - `Security Advisory TFV-4`_ |
| 309 | - `Security Advisory TFV-5`_ |
| 310 | - `Security Advisory TFV-6`_ |
| 311 | - `Security Advisory TFV-7`_ |
| 312 | - `Security Advisory TFV-8`_ |
| 313 | |
| 314 | |
| 315 | -------------- |
| 316 | |
| 317 | *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* |
| 318 | |
| 319 | .. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile |
| 320 | .. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php |
| 321 | .. _Power State Coordination Interface (PSCI): PSCI_ |
| 322 | .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf |
| 323 | .. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a |
| 324 | .. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf |
| 325 | .. _System Control and Management Interface (SCMI): SCMI_ |
| 326 | .. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf |
| 327 | .. _Software Delegated Exception Interface (SDEI): SDEI_ |
| 328 | .. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf |
| 329 | .. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php |
| 330 | .. _Arm FVP website: FVP_ |
| 331 | .. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms |
| 332 | .. _Linaro Release 18.04: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease18.04 |
| 333 | .. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os |
| 334 | .. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary |
| 335 | .. _Trusty Secure OS: https://source.android.com/security/trusty |
| 336 | .. _trustedfirmware.org: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git |
| 337 | .. _issue tracker: https://developer.trustedfirmware.org/project/board/1/ |
| 338 | .. _Security Center: ./docs/security-center.rst |
| 339 | .. _license: ./license.rst |
| 340 | .. _Contributing Guidelines: ./contributing.rst |
| 341 | .. _Acknowledgments: ./acknowledgements.rst |
| 342 | .. _Firmware Design: ./docs/firmware-design.rst |
| 343 | .. _Change Log: ./docs/change-log.rst |
| 344 | .. _User Guide: ./docs/user-guide.rst |
| 345 | .. _Porting Guide: ./docs/porting-guide.rst |
| 346 | .. _FreeBSD: http://www.freebsd.org |
| 347 | .. _SCC: http://www.simple-cc.org/ |
| 348 | .. _Security Advisory TFV-1: ./docs/security_advisories/security-advisory-tfv-1.rst |
| 349 | .. _Security Advisory TFV-2: ./docs/security_advisories/security-advisory-tfv-2.rst |
| 350 | .. _Security Advisory TFV-3: ./docs/security_advisories/security-advisory-tfv-3.rst |
| 351 | .. _Security Advisory TFV-4: ./docs/security_advisories/security-advisory-tfv-4.rst |
| 352 | .. _Security Advisory TFV-5: ./docs/security_advisories/security-advisory-tfv-5.rst |
| 353 | .. _Security Advisory TFV-6: ./docs/security_advisories/security-advisory-tfv-6.rst |
| 354 | .. _Security Advisory TFV-7: ./docs/security_advisories/security-advisory-tfv-7.rst |
| 355 | .. _Security Advisory TFV-8: ./docs/security_advisories/security-advisory-tfv-8.rst |
| 356 | .. _Trusted Firmware-A Documentation Contents: ./docs/contents.rst |