blob: f30eb287ddbe23abf013d56fcc60a4cb6e5a1d96 [file] [log] [blame]
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00001/*
Remi Pommareldb289172019-04-04 23:12:56 +02002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Carlo Caione56e98632019-08-28 10:14:46 +01007#ifndef GXL_DEF_H
8#define GXL_DEF_H
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00009
10#include <lib/utils_def.h>
11
12/*******************************************************************************
13 * System oscillator
14 ******************************************************************************/
Carlo Caione1e3e33b2019-08-28 15:32:22 +010015#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000016
17/*******************************************************************************
18 * Memory regions
19 ******************************************************************************/
Carlo Caione1e3e33b2019-08-28 15:32:22 +010020#define AML_NSDRAM0_BASE UL(0x01000000)
21#define AML_NSDRAM0_SIZE UL(0x0F000000)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000022
Carlo Caione1e3e33b2019-08-28 15:32:22 +010023#define AML_NSDRAM1_BASE UL(0x10000000)
24#define AML_NSDRAM1_SIZE UL(0x00100000)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000025
26#define BL31_BASE UL(0x05100000)
27#define BL31_SIZE UL(0x000C0000)
28#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
29
30/* Shared memory used for SMC services */
Carlo Caione107df3e2019-08-26 13:04:12 +010031#define AML_SHARE_MEM_INPUT_BASE UL(0x050FE000)
32#define AML_SHARE_MEM_OUTPUT_BASE UL(0x050FF000)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000033
Carlo Caione1e3e33b2019-08-28 15:32:22 +010034#define AML_SEC_DEVICE0_BASE UL(0xC0000000)
35#define AML_SEC_DEVICE0_SIZE UL(0x09000000)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000036
Carlo Caione1e3e33b2019-08-28 15:32:22 +010037#define AML_SEC_DEVICE1_BASE UL(0xD0040000)
38#define AML_SEC_DEVICE1_SIZE UL(0x00008000)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000039
Carlo Caione1e3e33b2019-08-28 15:32:22 +010040#define AML_TZRAM_BASE UL(0xD9000000)
41#define AML_TZRAM_SIZE UL(0x00014000)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000042/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
43
44/* Mailboxes */
Carlo Caione9c85f252019-08-28 09:46:18 +010045#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
46#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
Carlo Caione883e3ca2019-08-28 15:19:56 +010047#define AML_PSCI_MAILBOX_BASE UL(0xD9013F00)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000048
49// * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3)
50// * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) *
51// * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) *
52
Carlo Caione1e3e33b2019-08-28 15:32:22 +010053#define AML_TZROM_BASE UL(0xD9040000)
54#define AML_TZROM_SIZE UL(0x00010000)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000055
Carlo Caione1e3e33b2019-08-28 15:32:22 +010056#define AML_SEC_DEVICE2_BASE UL(0xDA000000)
57#define AML_SEC_DEVICE2_SIZE UL(0x00200000)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000058
Carlo Caione1e3e33b2019-08-28 15:32:22 +010059#define AML_SEC_DEVICE3_BASE UL(0xDA800000)
60#define AML_SEC_DEVICE3_SIZE UL(0x00200000)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000061
62/*******************************************************************************
63 * GIC-400 and interrupt handling related constants
64 ******************************************************************************/
Carlo Caione60c828b2019-08-24 18:51:48 +010065#define AML_GICD_BASE UL(0xC4301000)
66#define AML_GICC_BASE UL(0xC4302000)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000067
68#define IRQ_SEC_PHY_TIMER 29
69
70#define IRQ_SEC_SGI_0 8
71#define IRQ_SEC_SGI_1 9
72#define IRQ_SEC_SGI_2 10
73#define IRQ_SEC_SGI_3 11
74#define IRQ_SEC_SGI_4 12
75#define IRQ_SEC_SGI_5 13
76#define IRQ_SEC_SGI_6 14
77#define IRQ_SEC_SGI_7 15
78
79/*******************************************************************************
80 * UART definitions
81 ******************************************************************************/
Carlo Caione1afdfb02019-08-24 18:47:06 +010082#define AML_UART0_AO_BASE UL(0xC81004C0)
Carlo Caione1e3e33b2019-08-28 15:32:22 +010083#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ
Carlo Caione1afdfb02019-08-24 18:47:06 +010084#define AML_UART_BAUDRATE U(115200)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000085
86/*******************************************************************************
87 * Memory-mapped I/O Registers
88 ******************************************************************************/
Carlo Caione1e3e33b2019-08-28 15:32:22 +010089#define AML_AO_TIMESTAMP_CNTL UL(0xC81000B4)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000090
Carlo Caione1e3e33b2019-08-28 15:32:22 +010091#define AML_SYS_CPU_CFG7 UL(0xC8834664)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000092
Carlo Caione883e3ca2019-08-28 15:19:56 +010093#define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C)
Carlo Caione1e3e33b2019-08-28 15:32:22 +010094#define AML_AO_RTI_SCP_STAT UL(0xDA10023C)
95#define AML_AO_RTI_SCP_READY_OFF U(0x14)
96#define AML_A0_RTI_SCP_READY_MASK U(3)
97#define AML_AO_RTI_SCP_IS_READY(v) \
98 ((((v) >> AML_AO_RTI_SCP_READY_OFF) & \
99 AML_A0_RTI_SCP_READY_MASK) == AML_A0_RTI_SCP_READY_MASK)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000100
Carlo Caione9c85f252019-08-28 09:46:18 +0100101#define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404)
102#define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
103#define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
104#define AML_HIU_MAILBOX_SET_3 UL(0xDA83C428)
105#define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
106#define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000107
Carlo Caionedc52a052019-09-18 10:12:35 +0100108#define AML_SHA_DMA_BASE UL(0xC883E000)
109#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08)
110#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18)
111
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000112/*******************************************************************************
113 * System Monitor Call IDs and arguments
114 ******************************************************************************/
Carlo Caione107df3e2019-08-26 13:04:12 +0100115#define AML_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020)
116#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000117
Carlo Caione107df3e2019-08-26 13:04:12 +0100118#define AML_SM_EFUSE_READ U(0x82000030)
119#define AML_SM_EFUSE_USER_MAX U(0x82000033)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000120
Carlo Caione107df3e2019-08-26 13:04:12 +0100121#define AML_SM_JTAG_ON U(0x82000040)
122#define AML_SM_JTAG_OFF U(0x82000041)
Carlo Caionef7c4f9b2019-09-16 12:13:49 +0100123#define AML_SM_GET_CHIP_ID U(0x82000044)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000124
Carlo Caione107df3e2019-08-26 13:04:12 +0100125#define AML_JTAG_STATE_ON U(0)
126#define AML_JTAG_STATE_OFF U(1)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000127
Carlo Caione107df3e2019-08-26 13:04:12 +0100128#define AML_JTAG_M3_AO U(0)
129#define AML_JTAG_M3_EE U(1)
130#define AML_JTAG_A53_AO U(2)
131#define AML_JTAG_A53_EE U(3)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000132
Carlo Caione56e98632019-08-28 10:14:46 +0100133#endif /* GXL_DEF_H */