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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Varun Wadekar84a775e2019-01-03 10:12:55 -08002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
Varun Wadekarb7b45752015-12-28 14:55:41 -08007#include <arch_helpers.h>
Varun Wadekarf07d6de2018-02-27 14:33:57 -08008#include <assert.h>
Sam Payne71ce6ed2017-05-08 12:42:49 -07009#include <cortex_a57.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/bl_common.h>
Varun Wadekar4538bfc2019-01-02 17:53:15 -080011#include <common/debug.h>
12#include <common/interrupt_props.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <drivers/console.h>
14#include <lib/xlat_tables/xlat_tables_v2.h>
Varun Wadekar4538bfc2019-01-02 17:53:15 -080015#include <drivers/arm/gic_common.h>
16#include <drivers/arm/gicv2.h>
17#include <bl31/interrupt_mgmt.h>
18
19#include <bpmp.h>
20#include <flowctrl.h>
Varun Wadekar6e29d4d2018-03-07 11:13:58 -080021#include <memctrl.h>
Ambroise Vincentffbf32a2019-03-28 09:01:18 +000022#include <plat/common/platform.h>
Marvin Hsu21eea972017-04-11 11:00:48 +080023#include <security_engine.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053024#include <tegra_def.h>
Marvin Hsu21eea972017-04-11 11:00:48 +080025#include <tegra_platform.h>
Varun Wadekarb7b45752015-12-28 14:55:41 -080026#include <tegra_private.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053027
Varun Wadekarb316e242015-05-19 16:48:04 +053028/* sets of MMIO ranges setup */
29#define MMIO_RANGE_0_ADDR 0x50000000
30#define MMIO_RANGE_1_ADDR 0x60000000
31#define MMIO_RANGE_2_ADDR 0x70000000
32#define MMIO_RANGE_SIZE 0x200000
33
34/*
35 * Table of regions to map using the MMU.
36 */
37static const mmap_region_t tegra_mmap[] = {
Varun Wadekar08554a62017-06-12 16:47:16 -070038 MAP_REGION_FLAT(TEGRA_IRAM_BASE, 0x40000, /* 256KB */
Varun Wadekara6a357f2017-05-05 09:20:59 -070039 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekarb316e242015-05-19 16:48:04 +053040 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
41 MT_DEVICE | MT_RW | MT_SECURE),
42 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
43 MT_DEVICE | MT_RW | MT_SECURE),
44 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
45 MT_DEVICE | MT_RW | MT_SECURE),
46 {0}
47};
48
49/*******************************************************************************
50 * Set up the pagetables as per the platform memory map & initialize the MMU
51 ******************************************************************************/
52const mmap_region_t *plat_get_mmio_map(void)
53{
Marvin Hsu21eea972017-04-11 11:00:48 +080054 /* Add the map region for security engine SE2 */
55 if (tegra_chipid_is_t210_b01()) {
56 mmap_add_region((uint64_t)TEGRA_SE2_BASE,
57 (uint64_t)TEGRA_SE2_BASE,
58 (uint64_t)TEGRA_SE2_RANGE_SIZE,
59 MT_DEVICE | MT_RW | MT_SECURE);
60 }
61
Varun Wadekarb316e242015-05-19 16:48:04 +053062 /* MMIO space */
63 return tegra_mmap;
64}
65
66/*******************************************************************************
Varun Wadekare34bc3d2017-04-28 08:43:33 -070067 * The Tegra power domain tree has a single system level power domain i.e. a
68 * single root node. The first entry in the power domain descriptor specifies
69 * the number of power domains at the highest power level.
70 *******************************************************************************
71 */
72const unsigned char tegra_power_domain_tree_desc[] = {
73 /* No of root nodes */
74 1,
75 /* No of clusters */
76 PLATFORM_CLUSTER_COUNT,
77 /* No of CPU cores - cluster0 */
78 PLATFORM_MAX_CPUS_PER_CLUSTER,
79 /* No of CPU cores - cluster1 */
80 PLATFORM_MAX_CPUS_PER_CLUSTER
81};
82
83/*******************************************************************************
84 * This function returns the Tegra default topology tree information.
85 ******************************************************************************/
86const unsigned char *plat_get_power_domain_tree_desc(void)
87{
88 return tegra_power_domain_tree_desc;
89}
90
91/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +053092 * Handler to get the System Counter Frequency
93 ******************************************************************************/
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010094unsigned int plat_get_syscnt_freq2(void)
Varun Wadekarb316e242015-05-19 16:48:04 +053095{
96 return 19200000;
97}
Varun Wadekard2014c62015-10-29 10:37:28 +053098
99/*******************************************************************************
100 * Maximum supported UART controllers
101 ******************************************************************************/
102#define TEGRA210_MAX_UART_PORTS 5
103
104/*******************************************************************************
105 * This variable holds the UART port base addresses
106 ******************************************************************************/
107static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = {
108 0, /* undefined - treated as an error case */
109 TEGRA_UARTA_BASE,
110 TEGRA_UARTB_BASE,
111 TEGRA_UARTC_BASE,
112 TEGRA_UARTD_BASE,
113 TEGRA_UARTE_BASE,
114};
115
116/*******************************************************************************
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700117 * Enable console corresponding to the console ID
Varun Wadekard2014c62015-10-29 10:37:28 +0530118 ******************************************************************************/
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700119void plat_enable_console(int32_t id)
Varun Wadekard2014c62015-10-29 10:37:28 +0530120{
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700121 static console_16550_t uart_console;
122 uint32_t console_clock;
123
124 if ((id > 0) && (id < TEGRA210_MAX_UART_PORTS)) {
125 /*
126 * Reference clock used by the FPGAs is a lot slower.
127 */
128 if (tegra_platform_is_fpga()) {
129 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
130 } else {
131 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
132 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530133
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700134 (void)console_16550_register(tegra210_uart_addresses[id],
135 console_clock,
136 TEGRA_CONSOLE_BAUDRATE,
137 &uart_console);
138 console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
139 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
140 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530141}
Varun Wadekarb7b45752015-12-28 14:55:41 -0800142
143/*******************************************************************************
Marvin Hsu21eea972017-04-11 11:00:48 +0800144 * Handler for early platform setup
145 ******************************************************************************/
146void plat_early_platform_setup(void)
147{
Sam Payne71ce6ed2017-05-08 12:42:49 -0700148 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
149 uint64_t val;
150
151 /* platform parameter passed by the previous bootloader */
152 if (plat_params->l2_ecc_parity_prot_dis != 1) {
153 /* Enable ECC Parity Protection for Cortex-A57 CPUs */
154 val = read_l2ctlr_el1();
155 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
156 write_l2ctlr_el1(val);
157 }
158
Marvin Hsu21eea972017-04-11 11:00:48 +0800159 /* Initialize security engine driver */
160 if (tegra_chipid_is_t210_b01()) {
161 tegra_se_init();
162 }
163}
164
Varun Wadekar4538bfc2019-01-02 17:53:15 -0800165/* Secure IRQs for Tegra186 */
166static const interrupt_prop_t tegra210_interrupt_props[] = {
167 INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, GIC_HIGHEST_SEC_PRIORITY,
168 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
169};
170
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800171void plat_late_platform_setup(void)
172{
173 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
Varun Wadekar6e29d4d2018-03-07 11:13:58 -0800174 uint64_t sc7entry_end, offset;
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800175 int ret;
Varun Wadekara8c61ac2018-03-12 15:11:55 -0700176 uint32_t val;
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800177
178 /* memmap TZDRAM area containing the SC7 Entry Firmware */
179 if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) {
180
Varun Wadekardae27962018-03-05 10:19:37 -0800181 assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_A_SIZE);
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800182
183 /*
184 * Verify that the SC7 entry firmware resides inside the TZDRAM
Varun Wadekar6e29d4d2018-03-07 11:13:58 -0800185 * aperture, _before_ the BL31 code and the start address is
186 * exactly 1MB from BL31 base.
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800187 */
Varun Wadekar6e29d4d2018-03-07 11:13:58 -0800188
189 /* sc7entry-fw must be _before_ BL31 base */
190 assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base);
191
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800192 sc7entry_end = plat_params->sc7entry_fw_base +
193 plat_params->sc7entry_fw_size;
Varun Wadekar6e29d4d2018-03-07 11:13:58 -0800194 assert(sc7entry_end < plat_params->tzdram_base);
195
196 /* sc7entry-fw start must be exactly 1MB behind BL31 base */
197 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
198 assert(offset == 0x100000);
199
200 /* secure TZDRAM area */
201 tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
202 plat_params->tzdram_size + offset);
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800203
204 /* power off BPMP processor until SC7 entry */
205 tegra_fc_bpmp_off();
206
207 /* memmap SC7 entry firmware code */
208 ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base,
209 plat_params->sc7entry_fw_base,
210 plat_params->sc7entry_fw_size,
Varun Wadekar6e29d4d2018-03-07 11:13:58 -0800211 MT_SECURE | MT_RO_DATA);
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800212 assert(ret == 0);
Varun Wadekara8c61ac2018-03-12 15:11:55 -0700213
214 /* restrict PMC access to secure world */
215 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
216 val |= PMC_SECURITY_EN_BIT;
217 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
Varun Wadekarf07d6de2018-02-27 14:33:57 -0800218 }
219}
220
Marvin Hsu21eea972017-04-11 11:00:48 +0800221/*******************************************************************************
Varun Wadekarb7b45752015-12-28 14:55:41 -0800222 * Initialize the GIC and SGIs
223 ******************************************************************************/
224void plat_gic_setup(void)
225{
Varun Wadekar4538bfc2019-01-02 17:53:15 -0800226 tegra_gic_setup(tegra210_interrupt_props, ARRAY_SIZE(tegra210_interrupt_props));
Varun Wadekar84a775e2019-01-03 10:12:55 -0800227 tegra_gic_init();
Varun Wadekar4538bfc2019-01-02 17:53:15 -0800228
229 /* Enable handling for FIQs */
230 tegra_fiq_handler_setup();
231
232 /*
233 * Enable routing watchdog FIQs from the flow controller to
234 * the GICD.
235 */
236 tegra_fc_enable_fiq_to_ccplex_routing();
Varun Wadekarb7b45752015-12-28 14:55:41 -0800237}