blob: 02c640b535fbfb703d1e19dae714f873ea3771eb [file] [log] [blame]
Bai Ping06e325e2018-10-28 00:12:34 +08001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Bai Ping06e325e2018-10-28 00:12:34 +08007#include <stdlib.h>
8#include <stdint.h>
9#include <stdbool.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <common/debug.h>
12#include <lib/mmio.h>
13#include <lib/psci/psci.h>
14#include <platform_def.h>
15#include <services/std_svc.h>
16
17#include <gpc.h>
Bai Ping06e325e2018-10-28 00:12:34 +080018
Bai Ping06e325e2018-10-28 00:12:34 +080019/* use wfi power down the core */
20void imx_set_cpu_pwr_off(unsigned int core_id)
21{
22 /* enable the wfi power down of the core */
23 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
24 (1 << (core_id + 20)));
25 /* assert the pcg pcr bit of the core */
26 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
27};
28
Bai Ping06e325e2018-10-28 00:12:34 +080029/* if out of lpm, we need to do reverse steps */
30void imx_set_cpu_lpm(unsigned int core_id, bool pdn)
31{
32 if (pdn) {
33 /* enable the core WFI PDN & IRQ PUP */
34 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
35 (1 << (core_id + 20)) | COREx_IRQ_WUP(core_id));
36 /* assert the pcg pcr bit of the core */
37 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
38 } else {
39 /* disable CORE WFI PDN & IRQ PUP */
40 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
41 COREx_IRQ_WUP(core_id));
42 /* deassert the pcg pcr bit of the core */
43 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
44 }
45}
46
Bai Ping06e325e2018-10-28 00:12:34 +080047void imx_pup_pdn_slot_config(int last_core, bool pdn)
48{
49 if (pdn) {
50 /* SLOT0 for A53 PLAT power down */
51 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), SLT_PLAT_PDN);
52 /* SLOT1 for A53 PLAT power up */
53 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(1), SLT_PLAT_PUP);
54 /* SLOT2 for A53 primary core power up */
55 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(2), SLT_COREx_PUP(last_core));
56 /* ACK setting: PLAT ACK for PDN, CORE ACK for PUP */
57 mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF,
58 A53_PLAT_PDN_ACK | A53_PLAT_PUP_ACK);
59 } else {
60 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), 0xFFFFFFFF);
61 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), 0xFFFFFFFF);
62 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(2), 0xFFFFFFFF);
63 mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF,
64 A53_DUMMY_PDN_ACK | A53_DUMMY_PUP_ACK);
65 }
66}
67
Bai Ping06e325e2018-10-28 00:12:34 +080068void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state)
69{
70 uint32_t val;
71
72 if (is_local_state_off(power_state)) {
73 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
74 val |= A53_LPM_STOP; /* enable C0-C1's STOP mode */
75 val &= ~CPU_CLOCK_ON_LPM; /* disable CPU clock in LPM mode */
76 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
77
78 /* enable C2-3's STOP mode */
79 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_STOP);
80
81 /* enable PLAT/SCU power down */
82 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);
83 val &= ~EN_L2_WFI_PDN;
84 val |= L2PGE | EN_PLAT_PDN;
85 val &= ~COREx_IRQ_WUP(last_core); /* disable IRQ PUP for last core */
86 val |= COREx_LPM_PUP(last_core); /* enable LPM PUP for last core */
87 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);
88
89 imx_pup_pdn_slot_config(last_core, true);
90
91 /* enable PLAT PGC */
92 mmio_setbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1);
93 } else {
94 /* clear PLAT PGC */
95 mmio_clrbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1);
96
97 /* clear the slot and ack for cluster power down */
98 imx_pup_pdn_slot_config(last_core, false);
99
100 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
101 val &= ~A53_LPM_MASK; /* clear the C0~1 LPM */
102 val |= CPU_CLOCK_ON_LPM; /* disable cpu clock in LPM */
103 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
104
105 /* set A53 LPM to RUN mode */
106 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_MASK);
107
108 /* clear PLAT/SCU power down */
109 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);
110 val |= EN_L2_WFI_PDN;
111 val &= ~(L2PGE | EN_PLAT_PDN);
112 val &= ~COREx_LPM_PUP(last_core); /* disable C0's LPM PUP */
113 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);
114 }
115}
116
Bai Ping06e325e2018-10-28 00:12:34 +0800117void imx_gpc_init(void)
118{
119 uint32_t val;
120 int i;
121 /* mask all the interrupt by default */
122 /* Due to the hardware design requirement, need to make
123 * sure GPR interrupt(#32) is unmasked during RUN mode to
124 * avoid entering DSM mode by mistake.
125 */
126 for (i = 0; i < 4; i++) {
127 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, 0xFFFFFFFE);
128 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, 0xFFFFFFFE);
129 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, 0xFFFFFFFE);
130 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, 0xFFFFFFFE);
131 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
132 }
133
134 /* use external IRQs to wakeup C0~C3 from LPM */
135 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
136 val |= IRQ_SRC_A53_WUP;
137 /* clear the MASTER0 LPM handshake */
138 val &= ~MASTER0_LPM_HSK;
139 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
140
141 /* mask M4 DSM trigger if M4 is NOT enabled */
142 mmio_setbits_32(IMX_GPC_BASE + LPCR_M4, DSM_MODE_MASK);
143
144 /* set all mix/PU in A53 domain */
145 mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd);
146
147 /* set SCU timming */
148 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
149 (0x59 << 10) | 0x5B | (0x2 << 20));
150
151 /* set DUMMY PDN/PUP ACK by default for A53 domain */
152 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK |
153 A53_DUMMY_PDN_ACK);
154
155 /* disable DSM mode by default */
156 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, DSM_MODE_MASK);
157
158 /*
159 * USB PHY power up needs to make sure RESET bit in SRC is clear,
160 * otherwise, the PU power up bit in GPC will NOT self-cleared.
161 * only need to do it once.
162 */
163 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
164 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
165}