| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
| Roberto Vargas | 1a6eed3 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 7 | #ifndef FVP_PWRC_H |
| 8 | #define FVP_PWRC_H |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | |
| 10 | /* FVP Power controller register offset etc */ |
| Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 11 | #define PPOFFR_OFF U(0x0) |
| 12 | #define PPONR_OFF U(0x4) |
| 13 | #define PCOFFR_OFF U(0x8) |
| 14 | #define PWKUPR_OFF U(0xc) |
| 15 | #define PSYSR_OFF U(0x10) |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 16 | |
| Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 17 | #define PWKUPR_WEN BIT_32(31) |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 18 | |
| Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 19 | #define PSYSR_AFF_L2 BIT_32(31) |
| 20 | #define PSYSR_AFF_L1 BIT_32(30) |
| 21 | #define PSYSR_AFF_L0 BIT_32(29) |
| 22 | #define PSYSR_WEN BIT_32(28) |
| 23 | #define PSYSR_PC BIT_32(27) |
| 24 | #define PSYSR_PP BIT_32(26) |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 25 | |
| 26 | #define PSYSR_WK_SHIFT 24 |
| Soby Mathew | 2ae2319 | 2015-04-30 12:27:41 +0100 | [diff] [blame] | 27 | #define PSYSR_WK_WIDTH 0x2 |
| Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 28 | #define PSYSR_WK_MASK ((1U << PSYSR_WK_WIDTH) - 1U) |
| 29 | #define PSYSR_WK(x) ((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 30 | |
| Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 31 | #define WKUP_COLD U(0x0) |
| 32 | #define WKUP_RESET U(0x1) |
| 33 | #define WKUP_PPONR U(0x2) |
| 34 | #define WKUP_GICREQ U(0x3) |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 35 | |
| Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 36 | #define PSYSR_INVALID U(0xffffffff) |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 37 | |
| 38 | #ifndef __ASSEMBLY__ |
| 39 | |
| Antonio Nino Diaz | f13d09a | 2019-01-23 21:50:09 +0000 | [diff] [blame] | 40 | #include <stdint.h> |
| 41 | |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 42 | /******************************************************************************* |
| 43 | * Function & variable prototypes |
| 44 | ******************************************************************************/ |
| Roberto Vargas | 1a6eed3 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 45 | void fvp_pwrc_write_pcoffr(u_register_t mpidr); |
| 46 | void fvp_pwrc_write_ppoffr(u_register_t mpidr); |
| 47 | void fvp_pwrc_write_pponr(u_register_t mpidr); |
| 48 | void fvp_pwrc_set_wen(u_register_t mpidr); |
| 49 | void fvp_pwrc_clr_wen(u_register_t mpidr); |
| 50 | unsigned int fvp_pwrc_read_psysr(u_register_t mpidr); |
| 51 | unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr); |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 52 | |
| 53 | #endif /*__ASSEMBLY__*/ |
| 54 | |
| Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 55 | #endif /* FVP_PWRC_H */ |