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Antonio Nino Diaz272e8712018-09-18 01:36:00 +01001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef GXBB_DEF_H
8#define GXBB_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010011
12/*******************************************************************************
13 * System oscillator
14 ******************************************************************************/
15#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
16
17/*******************************************************************************
18 * Memory regions
19 ******************************************************************************/
20#define GXBB_NSDRAM0_BASE UL(0x01000000)
21#define GXBB_NSDRAM0_SIZE UL(0x0F000000)
22
23#define GXBB_NSDRAM1_BASE UL(0x10000000)
24#define GXBB_NSDRAM1_SIZE UL(0x00100000)
25
26#define BL31_BASE UL(0x10100000)
27#define BL31_SIZE UL(0x000C0000)
28#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
29
30/* Shared memory used for SMC services */
31#define GXBB_SHARE_MEM_INPUT_BASE UL(0x100FE000)
32#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x100FF000)
33
34#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000)
35#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000)
36
37#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000)
38#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000)
39
40#define GXBB_TZRAM_BASE UL(0xD9000000)
41#define GXBB_TZRAM_SIZE UL(0x00014000)
42/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
43
44/* Mailboxes */
45#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
46#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
47#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00)
48
49#define GXBB_TZROM_BASE UL(0xD9040000)
50#define GXBB_TZROM_SIZE UL(0x00010000)
51
52#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000)
53#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000)
54
55#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000)
56#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000)
57
58/*******************************************************************************
59 * GIC-400 and interrupt handling related constants
60 ******************************************************************************/
61#define GXBB_GICD_BASE UL(0xC4301000)
62#define GXBB_GICC_BASE UL(0xC4302000)
63
64#define IRQ_SEC_PHY_TIMER 29
65
66#define IRQ_SEC_SGI_0 8
67#define IRQ_SEC_SGI_1 9
68#define IRQ_SEC_SGI_2 10
69#define IRQ_SEC_SGI_3 11
70#define IRQ_SEC_SGI_4 12
71#define IRQ_SEC_SGI_5 13
72#define IRQ_SEC_SGI_6 14
73#define IRQ_SEC_SGI_7 15
74
75/*******************************************************************************
76 * UART definitions
77 ******************************************************************************/
78#define GXBB_UART0_AO_BASE UL(0xC81004C0)
79#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ
80#define GXBB_UART_BAUDRATE U(115200)
81
82/*******************************************************************************
83 * Memory-mapped I/O Registers
84 ******************************************************************************/
85#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4)
86
87#define GXBB_SYS_CPU_CFG7 UL(0xC8834664)
88
89#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C)
90
91#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404)
92#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
93#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
94#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428)
95#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
96#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
97
98/*******************************************************************************
99 * System Monitor Call IDs and arguments
100 ******************************************************************************/
101#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020)
102#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021)
103
104#define GXBB_SM_EFUSE_READ U(0x82000030)
105#define GXBB_SM_EFUSE_USER_MAX U(0x82000033)
106
107#define GXBB_SM_JTAG_ON U(0x82000040)
108#define GXBB_SM_JTAG_OFF U(0x82000041)
109
110#define GXBB_JTAG_STATE_ON U(0)
111#define GXBB_JTAG_STATE_OFF U(1)
112
113#define GXBB_JTAG_M3_AO U(0)
114#define GXBB_JTAG_M3_EE U(1)
115#define GXBB_JTAG_A53_AO U(2)
116#define GXBB_JTAG_A53_EE U(3)
117
118#endif /* GXBB_DEF_H */