| Usama Arif | e97998f | 2018-11-30 15:43:56 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2019, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef FVP_VE_DEF_H |
| 8 | #define FVP_VE_DEF_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | /* Default cluster count for FVP VE */ |
| 13 | #define FVP_VE_CLUSTER_COUNT 1 |
| 14 | |
| 15 | /* Default number of CPUs per cluster on FVP VE */ |
| 16 | #define FVP_VE_MAX_CPUS_PER_CLUSTER 1 |
| 17 | |
| 18 | /* Default number of threads per CPU on FVP VE */ |
| 19 | #define FVP_VE_MAX_PE_PER_CPU 1 |
| 20 | |
| 21 | #define FVP_VE_CORE_COUNT 1 |
| 22 | |
| 23 | #define FVP_VE_PRIMARY_CPU 0x0 |
| 24 | |
| 25 | /******************************************************************************* |
| 26 | * FVP memory map related constants |
| 27 | ******************************************************************************/ |
| 28 | |
| 29 | #define FLASH1_BASE 0x0c000000 |
| 30 | #define FLASH1_SIZE 0x04000000 |
| 31 | |
| 32 | /* Aggregate of all devices in the first GB */ |
| 33 | #define DEVICE0_BASE 0x20000000 |
| 34 | #define DEVICE0_SIZE 0x0c200000 |
| 35 | |
| 36 | #define NSRAM_BASE 0x2e000000 |
| 37 | #define NSRAM_SIZE 0x10000 |
| 38 | |
| 39 | #define PCIE_EXP_BASE 0x40000000 |
| 40 | #define TZRNG_BASE 0x7fe60000 |
| 41 | |
| 42 | #define ARCH_MODEL_VE 0x5 |
| 43 | |
| 44 | /* FVP Power controller base address*/ |
| 45 | #define PWRC_BASE UL(0x1c100000) |
| 46 | |
| 47 | /* FVP SP804 timer frequency is 35 MHz*/ |
| 48 | #define SP804_TIMER_CLKMULT 1 |
| 49 | #define SP804_TIMER_CLKDIV 35 |
| 50 | |
| 51 | /* SP810 controller. FVP specific flags */ |
| 52 | #define FVP_SP810_CTRL_TIM0_OV (1 << 16) |
| 53 | #define FVP_SP810_CTRL_TIM1_OV (1 << 18) |
| 54 | #define FVP_SP810_CTRL_TIM2_OV (1 << 20) |
| 55 | #define FVP_SP810_CTRL_TIM3_OV (1 << 22) |
| 56 | |
| 57 | /******************************************************************************* |
| 58 | * GIC-400 & interrupt handling related constants |
| 59 | ******************************************************************************/ |
| 60 | /* VE compatible GIC memory map */ |
| 61 | #define VE_GICD_BASE 0x2c001000 |
| 62 | #define VE_GICC_BASE 0x2c002000 |
| 63 | #define VE_GICH_BASE 0x2c004000 |
| 64 | #define VE_GICV_BASE 0x2c006000 |
| 65 | |
| 66 | #define FVP_VE_IRQ_TZ_WDOG 56 |
| 67 | #define FVP_VE_IRQ_SEC_SYS_TIMER 57 |
| 68 | |
| 69 | #define V2M_FLASH1_BASE UL(0x0C000000) |
| 70 | #define V2M_FLASH1_SIZE UL(0x04000000) |
| 71 | |
| 72 | #define V2M_MAP_FLASH1_RW MAP_REGION_FLAT(V2M_FLASH1_BASE,\ |
| 73 | V2M_FLASH1_SIZE, \ |
| 74 | MT_DEVICE | MT_RW | MT_SECURE) |
| 75 | |
| 76 | #define V2M_MAP_FLASH1_RO MAP_REGION_FLAT(V2M_FLASH1_BASE,\ |
| 77 | V2M_FLASH1_SIZE, \ |
| 78 | MT_RO_DATA | MT_SECURE) |
| 79 | |
| 80 | #endif /* FVP_VE_DEF_H */ |