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Jeenu Viswambharan615ff392016-10-24 14:31:51 +01001#
Jeenu Viswambharanfca76802017-01-16 16:52:35 +00002# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
13# The AArch32 Secure Payload to be built as BL32 image
14AARCH32_SP := none
15
16# The Target build architecture. Supported values are: aarch64, aarch32.
17ARCH := aarch64
18
19# Determine the version of ARM CCI product used in the platform. The platform
20# port can change this value if needed.
21ARM_CCI_PRODUCT_ID := 400
22
Jeenu Viswambharanfca76802017-01-16 16:52:35 +000023# ARM Architecture major and minor versions: 8.0 by default.
24ARM_ARCH_MAJOR := 8
25ARM_ARCH_MINOR := 0
26
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010027# Determine the version of ARM GIC architecture to use for interrupt management
28# in EL3. The platform port can change this value if needed.
29ARM_GIC_ARCH := 2
30
31# Flag used to indicate if ASM_ASSERTION should be enabled for the build.
32ASM_ASSERTION := 0
33
34# Base commit to perform code check on
35BASE_COMMIT := origin/master
36
37# By default, consider that the platform may release several CPUs out of reset.
38# The platform Makefile is free to override this value.
39COLD_BOOT_SINGLE_CPU := 0
40
41# For Chain of Trust
42CREATE_KEYS := 1
43
44# Build flag to include AArch32 registers in cpu context save and restore during
45# world switch. This flag must be set to 0 for AArch64-only platforms.
46CTX_INCLUDE_AARCH32_REGS := 1
47
48# Include FP registers in cpu context
49CTX_INCLUDE_FPREGS := 0
50
51# Debug build
52DEBUG := 0
53
54# Build platform
55DEFAULT_PLAT := fvp
56
57# By default, use the -pedantic option in the gcc command line
58DISABLE_PEDANTIC := 0
59
60# Flag to enable Performance Measurement Framework
61ENABLE_PMF := 0
62
63# Flag to enable PSCI STATs functionality
64ENABLE_PSCI_STAT := 0
65
66# Flag to enable runtime instrumentation using PMF
67ENABLE_RUNTIME_INSTRUMENTATION := 0
68
Douglas Raillard306593d2017-02-24 18:14:15 +000069# Flag to enable stack corruption protection
70ENABLE_STACK_PROTECTOR := 0
71
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010072# Build flag to treat usage of deprecated platform and framework APIs as error.
73ERROR_DEPRECATED := 0
74
Masahiro Yamada4d87eb42016-12-25 13:52:22 +090075# Byte alignment that each component in FIP is aligned to
76FIP_ALIGN := 0
77
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010078# Default FIP file name
79FIP_NAME := fip.bin
80
81# Default FWU_FIP file name
82FWU_FIP_NAME := fwu_fip.bin
83
84# For Chain of Trust
85GENERATE_COT := 0
86
Jeenu Viswambharana10d64e2017-01-04 13:51:42 +000087# Whether system coherency is managed in hardware, without explicit software
88# operations.
89HW_ASSISTED_COHERENCY := 0
90
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010091# Flag to enable new version of image loading
92LOAD_IMAGE_V2 := 0
93
94# NS timer register save and restore
95NS_TIMER_SWITCH := 0
96
97# Build PL011 UART driver in minimal generic UART mode
98PL011_GENERIC_UART := 0
99
100# By default, consider that the platform's reset address is not programmable.
101# The platform Makefile is free to override this value.
102PROGRAMMABLE_RESET_ADDRESS := 0
103
104# Flag used to choose the power state format viz Extended State-ID or the
105# Original format.
106PSCI_EXTENDED_STATE_ID := 0
107
108# By default, BL1 acts as the reset handler, not BL31
109RESET_TO_BL31 := 0
110
111# For Chain of Trust
112SAVE_KEYS := 0
113
114# Whether code and read-only data should be put on separate memory pages. The
115# platform Makefile is free to override this value.
116SEPARATE_CODE_AND_RODATA := 0
117
118# SPD choice
119SPD := none
120
121# Flag to introduce an infinite loop in BL1 just before it exits into the next
122# image. This is meant to help debugging the post-BL2 phase.
123SPIN_ON_BL1_EXIT := 0
124
125# Flags to build TF with Trusted Boot support
126TRUSTED_BOARD_BOOT := 0
127
128# Build option to choose whether Trusted firmware uses Coherent memory or not.
129USE_COHERENT_MEM := 1
130
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900131# Use tbbr_oid.h instead of platform_oid.h
132USE_TBBR_DEFS = $(ERROR_DEPRECATED)
133
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100134# Build verbosity
135V := 0
Soby Mathew043fe9c2017-04-10 22:35:42 +0100136
137# Whether to enable D-Cache early during warm boot. This is usually
138# applicable for platforms wherein interconnect programming is not
139# required to enable cache coherency after warm reset (eg: single cluster
140# platforms).
141WARMBOOT_ENABLE_DCACHE_EARLY := 0