Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 1 | /* |
Khandelwal | 368564c | 2020-01-29 16:51:42 +0000 | [diff] [blame] | 2 | * Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | #include <lib/xlat_tables/xlat_tables_defs.h> |
| 12 | #include <plat/arm/board/common/v2m_def.h> |
| 13 | #include <plat/arm/common/arm_spm_def.h> |
Manish V Badarkhe | 5586151 | 2020-03-27 13:25:51 +0000 | [diff] [blame] | 14 | #include <plat/arm/common/smccc_def.h> |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 15 | #include <plat/common/common_def.h> |
| 16 | |
Vishnu Banavath | 5be00c0 | 2019-08-07 10:49:05 +0100 | [diff] [blame] | 17 | /* PL011 UART related constants */ |
| 18 | #ifdef V2M_IOFPGA_UART0_CLK_IN_HZ |
| 19 | #undef V2M_IOFPGA_UART0_CLK_IN_HZ |
| 20 | #endif |
| 21 | |
| 22 | #ifdef V2M_IOFPGA_UART1_CLK_IN_HZ |
| 23 | #undef V2M_IOFPGA_UART1_CLK_IN_HZ |
| 24 | #endif |
| 25 | |
| 26 | #define V2M_IOFPGA_UART0_CLK_IN_HZ 32000000 |
| 27 | #define V2M_IOFPGA_UART1_CLK_IN_HZ 32000000 |
| 28 | |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 29 | /* Core/Cluster/Thread counts for Corstone700 */ |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 30 | #define CORSTONE700_CLUSTER_COUNT U(1) |
| 31 | #define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4) |
| 32 | #define CORSTONE700_MAX_PE_PER_CPU U(1) |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 33 | |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 34 | #define PLAT_ARM_CLUSTER_COUNT CORSTONE700_CLUSTER_COUNT |
| 35 | |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 36 | #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ |
| 37 | CORSTONE700_MAX_CPUS_PER_CLUSTER * \ |
| 38 | CORSTONE700_MAX_PE_PER_CPU) |
| 39 | |
| 40 | |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 41 | /* UART related constants */ |
| 42 | #define PLAT_ARM_BOOT_UART_BASE 0x1a510000 |
| 43 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ |
| 44 | #define PLAT_ARM_RUN_UART_BASE 0x1a520000 |
| 45 | #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ |
| 46 | #define ARM_CONSOLE_BAUDRATE 115200 |
| 47 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE |
| 48 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ |
| 49 | |
| 50 | /* Memory related constants */ |
| 51 | #define ARM_DRAM1_BASE UL(0x80000000) |
| 52 | #define ARM_DRAM1_SIZE UL(0x80000000) |
| 53 | #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ |
| 54 | ARM_DRAM1_SIZE - 1) |
| 55 | #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE |
| 56 | #define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE |
| 57 | #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ |
| 58 | ARM_NS_DRAM1_SIZE - 1) |
| 59 | #define ARM_TRUSTED_SRAM_BASE UL(0x02000000) |
| 60 | #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE |
| 61 | #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ |
| 62 | #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ |
| 63 | |
| 64 | /* The remaining Trusted SRAM is used to load the BL images */ |
| 65 | #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ |
| 66 | ARM_SHARED_RAM_SIZE) |
| 67 | #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ |
| 68 | ARM_SHARED_RAM_SIZE) |
| 69 | |
| 70 | /* |
| 71 | * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding |
| 72 | * the page reserved for fw_configs) to BL32 |
| 73 | */ |
| 74 | #define BL32_BASE (ARM_BL_RAM_BASE + PAGE_SIZE) |
| 75 | #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 76 | |
| 77 | /* |
| 78 | * Some data must be aligned on the biggest cache line size in the platform. |
| 79 | * This is known only to the platform as it might have a combination of |
| 80 | * integrated and external caches. |
| 81 | */ |
| 82 | #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) |
| 83 | #define ARM_CACHE_WRITEBACK_SHIFT 6 |
| 84 | |
| 85 | /* |
| 86 | * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base |
| 87 | * and limit. Leave enough space for BL2 meminfo. |
| 88 | */ |
| 89 | #define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) |
| 90 | #define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U)) |
| 91 | |
| 92 | /* |
| 93 | * The max number of regions like RO(code), coherent and data required by |
| 94 | * different BL stages which need to be mapped in the MMU. |
| 95 | */ |
| 96 | #define ARM_BL_REGIONS 2 |
| 97 | #define PLAT_ARM_MMAP_ENTRIES 8 |
| 98 | #define MAX_XLAT_TABLES 5 |
| 99 | #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ |
| 100 | ARM_BL_REGIONS) |
| 101 | |
| 102 | /* GIC related constants */ |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 103 | #define PLAT_ARM_GICD_BASE 0x1C010000 |
| 104 | #define PLAT_ARM_GICC_BASE 0x1C02F000 |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 105 | |
Khandelwal | 368564c | 2020-01-29 16:51:42 +0000 | [diff] [blame] | 106 | /* MHUv2 Secure Channel receiver and sender */ |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 107 | #define PLAT_SDK700_MHU0_SEND 0x1B800000 |
| 108 | #define PLAT_SDK700_MHU0_RECV 0x1B810000 |
Khandelwal | 368564c | 2020-01-29 16:51:42 +0000 | [diff] [blame] | 109 | |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 110 | /* Timer/watchdog related constants */ |
| 111 | #define ARM_SYS_CNTCTL_BASE UL(0x1a200000) |
| 112 | #define ARM_SYS_CNTREAD_BASE UL(0x1a210000) |
| 113 | #define ARM_SYS_TIMCTL_BASE UL(0x1a220000) |
| 114 | #define CORSTONE700_TIMER_BASE_FREQUENCY UL(24000000) |
| 115 | #define CORSTONE700_IRQ_TZ_WDOG 32 |
| 116 | #define CORSTONE700_IRQ_SEC_SYS_TIMER 34 |
| 117 | |
| 118 | #define PLAT_MAX_PWR_LVL 2 |
| 119 | /* |
| 120 | * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The |
| 121 | * power levels have a 1:1 mapping with the MPIDR affinity levels. |
| 122 | */ |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 123 | #define ARM_PWR_LVL0 MPIDR_AFFLVL0 |
| 124 | #define ARM_PWR_LVL1 MPIDR_AFFLVL1 |
| 125 | #define ARM_PWR_LVL2 MPIDR_AFFLVL2 |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 126 | |
| 127 | /* |
| 128 | * Macros for local power states in ARM platforms encoded by State-ID field |
| 129 | * within the power-state parameter. |
| 130 | */ |
| 131 | /* Local power state for power domains in Run state. */ |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 132 | #define ARM_LOCAL_STATE_RUN U(0) |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 133 | /* Local power state for retention. Valid only for CPU power domains */ |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 134 | #define ARM_LOCAL_STATE_RET U(1) |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 135 | /* Local power state for OFF/power-down. Valid for CPU and cluster |
| 136 | * power domains |
| 137 | */ |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 138 | #define ARM_LOCAL_STATE_OFF U(2) |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 139 | |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 140 | #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE |
| 141 | #define PLAT_ARM_NSTIMER_FRAME_ID U(1) |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 142 | |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 143 | #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000)) |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 144 | |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 145 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 146 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 147 | |
| 148 | /* |
| 149 | * This macro defines the deepest retention state possible. A higher state |
| 150 | * ID will represent an invalid or a power down state. |
| 151 | */ |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 152 | #define PLAT_MAX_RET_STATE 1 |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 153 | |
| 154 | /* |
| 155 | * This macro defines the deepest power down states possible. Any state ID |
| 156 | * higher than this is invalid. |
| 157 | */ |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 158 | #define PLAT_MAX_OFF_STATE 2 |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 159 | |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 160 | #define PLATFORM_STACK_SIZE UL(0x440) |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 161 | |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 162 | #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 163 | ARM_SHARED_RAM_BASE, \ |
| 164 | ARM_SHARED_RAM_SIZE, \ |
| 165 | MT_DEVICE | MT_RW | MT_SECURE) |
| 166 | |
| 167 | #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ |
| 168 | ARM_NS_DRAM1_BASE, \ |
| 169 | ARM_NS_DRAM1_SIZE, \ |
| 170 | MT_MEMORY | MT_RW | MT_NS) |
| 171 | |
| 172 | #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ |
| 173 | BL_CODE_BASE, \ |
| 174 | BL_CODE_END \ |
| 175 | - BL_CODE_BASE, \ |
| 176 | MT_CODE | MT_SECURE), \ |
| 177 | MAP_REGION_FLAT( \ |
| 178 | BL_RO_DATA_BASE, \ |
| 179 | BL_RO_DATA_END \ |
| 180 | - BL_RO_DATA_BASE, \ |
| 181 | MT_RO_DATA | MT_SECURE) |
| 182 | #if USE_COHERENT_MEM |
| 183 | #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ |
| 184 | BL_COHERENT_RAM_BASE, \ |
| 185 | BL_COHERENT_RAM_END \ |
| 186 | - BL_COHERENT_RAM_BASE, \ |
| 187 | MT_DEVICE | MT_RW | MT_SECURE) |
| 188 | #endif |
| 189 | |
| 190 | #define CORSTONE700_DEVICE_BASE (0x1A000000) |
| 191 | #define CORSTONE700_DEVICE_SIZE (0x26000000) |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 192 | #define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \ |
| 193 | CORSTONE700_DEVICE_BASE,\ |
| 194 | CORSTONE700_DEVICE_SIZE,\ |
| 195 | MT_DEVICE | MT_RW | MT_SECURE) |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 196 | |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 197 | #define ARM_IRQ_SEC_PHY_TIMER 29 |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 198 | |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 199 | #define ARM_IRQ_SEC_SGI_0 8 |
| 200 | #define ARM_IRQ_SEC_SGI_1 9 |
| 201 | #define ARM_IRQ_SEC_SGI_2 10 |
| 202 | #define ARM_IRQ_SEC_SGI_3 11 |
| 203 | #define ARM_IRQ_SEC_SGI_4 12 |
| 204 | #define ARM_IRQ_SEC_SGI_5 13 |
| 205 | #define ARM_IRQ_SEC_SGI_6 14 |
| 206 | #define ARM_IRQ_SEC_SGI_7 15 |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 207 | |
| 208 | /* |
| 209 | * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 |
| 210 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 211 | * as Group 0 interrupts. |
| 212 | */ |
| 213 | #define ARM_G1S_IRQ_PROPS(grp) \ |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 214 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 215 | (grp), GIC_INTR_CFG_LEVEL), \ |
| 216 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ |
| 217 | (grp), GIC_INTR_CFG_EDGE), \ |
| 218 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ |
| 219 | (grp), GIC_INTR_CFG_EDGE), \ |
| 220 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ |
| 221 | (grp), GIC_INTR_CFG_EDGE), \ |
| 222 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ |
| 223 | (grp), GIC_INTR_CFG_EDGE), \ |
| 224 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ |
| 225 | (grp), GIC_INTR_CFG_EDGE), \ |
| 226 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ |
| 227 | (grp), GIC_INTR_CFG_EDGE) |
| 228 | |
| 229 | #define ARM_G0_IRQ_PROPS(grp) \ |
| 230 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
| 231 | GIC_INTR_CFG_EDGE) |
| 232 | |
| 233 | /* |
| 234 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 235 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 236 | * as Group 0 interrupts. |
| 237 | */ |
| 238 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
Avinash Mehta | d46b58c | 2019-07-11 16:23:43 +0100 | [diff] [blame] | 239 | ARM_G1S_IRQ_PROPS(grp), \ |
| 240 | INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \ |
| 241 | (grp), GIC_INTR_CFG_LEVEL), \ |
| 242 | INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \ |
| 243 | GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) |
Manish Pandey | 52990ae | 2018-11-28 11:20:37 +0000 | [diff] [blame] | 244 | |
| 245 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 246 | |
| 247 | #endif /* PLATFORM_DEF_H */ |