| Yann Gautier | f7fdf98 | 2019-05-27 14:20:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2024, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef STM32MP_RISAB_REGS_H |
| 8 | #define STM32MP_RISAB_REGS_H |
| 9 | |
| 10 | #define RISAB_CR U(0x00) |
| 11 | #define RISAB_IASR U(0x08) |
| 12 | #define RISAB_IACR U(0x0C) |
| 13 | #define RISAB_RIFLOCKR U(0x10) |
| 14 | #define RISAB_IAESR U(0x20) |
| 15 | #define RISAB_IADDR U(0x24) |
| 16 | #define RISAB_PG0_SECCFGR U(0x100) |
| 17 | #define RISAB_PG1_SECCFGR U(0x104) |
| 18 | #define RISAB_PG2_SECCFGR U(0x108) |
| 19 | #define RISAB_PG3_SECCFGR U(0x10C) |
| 20 | #define RISAB_PG4_SECCFGR U(0x110) |
| 21 | #define RISAB_PG5_SECCFGR U(0x114) |
| 22 | #define RISAB_PG6_SECCFGR U(0x118) |
| 23 | #define RISAB_PG7_SECCFGR U(0x11C) |
| 24 | #define RISAB_PG8_SECCFGR U(0x120) |
| 25 | #define RISAB_PG9_SECCFGR U(0x124) |
| 26 | #define RISAB_PG10_SECCFGR U(0x128) |
| 27 | #define RISAB_PG11_SECCFGR U(0x12C) |
| 28 | #define RISAB_PG12_SECCFGR U(0x130) |
| 29 | #define RISAB_PG13_SECCFGR U(0x134) |
| 30 | #define RISAB_PG14_SECCFGR U(0x138) |
| 31 | #define RISAB_PG15_SECCFGR U(0x13C) |
| 32 | #define RISAB_PG16_SECCFGR U(0x140) |
| 33 | #define RISAB_PG17_SECCFGR U(0x144) |
| 34 | #define RISAB_PG18_SECCFGR U(0x148) |
| 35 | #define RISAB_PG19_SECCFGR U(0x14C) |
| 36 | #define RISAB_PG20_SECCFGR U(0x150) |
| 37 | #define RISAB_PG21_SECCFGR U(0x154) |
| 38 | #define RISAB_PG22_SECCFGR U(0x158) |
| 39 | #define RISAB_PG23_SECCFGR U(0x15C) |
| 40 | #define RISAB_PG24_SECCFGR U(0x160) |
| 41 | #define RISAB_PG25_SECCFGR U(0x164) |
| 42 | #define RISAB_PG26_SECCFGR U(0x168) |
| 43 | #define RISAB_PG27_SECCFGR U(0x16C) |
| 44 | #define RISAB_PG28_SECCFGR U(0x170) |
| 45 | #define RISAB_PG29_SECCFGR U(0x174) |
| 46 | #define RISAB_PG30_SECCFGR U(0x178) |
| 47 | #define RISAB_PG31_SECCFGR U(0x17C) |
| 48 | #define RISAB_PG0_PRIVCFGR U(0x200) |
| 49 | #define RISAB_PG1_PRIVCFGR U(0x204) |
| 50 | #define RISAB_PG2_PRIVCFGR U(0x208) |
| 51 | #define RISAB_PG3_PRIVCFGR U(0x20C) |
| 52 | #define RISAB_PG4_PRIVCFGR U(0x210) |
| 53 | #define RISAB_PG5_PRIVCFGR U(0x214) |
| 54 | #define RISAB_PG6_PRIVCFGR U(0x218) |
| 55 | #define RISAB_PG7_PRIVCFGR U(0x21C) |
| 56 | #define RISAB_PG8_PRIVCFGR U(0x220) |
| 57 | #define RISAB_PG9_PRIVCFGR U(0x224) |
| 58 | #define RISAB_PG10_PRIVCFGR U(0x228) |
| 59 | #define RISAB_PG11_PRIVCFGR U(0x22C) |
| 60 | #define RISAB_PG12_PRIVCFGR U(0x230) |
| 61 | #define RISAB_PG13_PRIVCFGR U(0x234) |
| 62 | #define RISAB_PG14_PRIVCFGR U(0x238) |
| 63 | #define RISAB_PG15_PRIVCFGR U(0x23C) |
| 64 | #define RISAB_PG16_PRIVCFGR U(0x240) |
| 65 | #define RISAB_PG17_PRIVCFGR U(0x244) |
| 66 | #define RISAB_PG18_PRIVCFGR U(0x248) |
| 67 | #define RISAB_PG19_PRIVCFGR U(0x24C) |
| 68 | #define RISAB_PG20_PRIVCFGR U(0x250) |
| 69 | #define RISAB_PG21_PRIVCFGR U(0x254) |
| 70 | #define RISAB_PG22_PRIVCFGR U(0x258) |
| 71 | #define RISAB_PG23_PRIVCFGR U(0x25C) |
| 72 | #define RISAB_PG24_PRIVCFGR U(0x260) |
| 73 | #define RISAB_PG25_PRIVCFGR U(0x264) |
| 74 | #define RISAB_PG26_PRIVCFGR U(0x268) |
| 75 | #define RISAB_PG27_PRIVCFGR U(0x26C) |
| 76 | #define RISAB_PG28_PRIVCFGR U(0x270) |
| 77 | #define RISAB_PG29_PRIVCFGR U(0x274) |
| 78 | #define RISAB_PG30_PRIVCFGR U(0x278) |
| 79 | #define RISAB_PG31_PRIVCFGR U(0x27C) |
| 80 | #define RISAB_PG0_C2PRIVCFGR U(0x600) |
| 81 | #define RISAB_PG1_C2PRIVCFGR U(0x604) |
| 82 | #define RISAB_PG2_C2PRIVCFGR U(0x608) |
| 83 | #define RISAB_PG3_C2PRIVCFGR U(0x60C) |
| 84 | #define RISAB_PG4_C2PRIVCFGR U(0x610) |
| 85 | #define RISAB_PG5_C2PRIVCFGR U(0x614) |
| 86 | #define RISAB_PG6_C2PRIVCFGR U(0x618) |
| 87 | #define RISAB_PG7_C2PRIVCFGR U(0x61C) |
| 88 | #define RISAB_PG8_C2PRIVCFGR U(0x620) |
| 89 | #define RISAB_PG9_C2PRIVCFGR U(0x624) |
| 90 | #define RISAB_PG10_C2PRIVCFGR U(0x628) |
| 91 | #define RISAB_PG11_C2PRIVCFGR U(0x62C) |
| 92 | #define RISAB_PG12_C2PRIVCFGR U(0x630) |
| 93 | #define RISAB_PG13_C2PRIVCFGR U(0x634) |
| 94 | #define RISAB_PG14_C2PRIVCFGR U(0x638) |
| 95 | #define RISAB_PG15_C2PRIVCFGR U(0x63C) |
| 96 | #define RISAB_PG16_C2PRIVCFGR U(0x640) |
| 97 | #define RISAB_PG17_C2PRIVCFGR U(0x644) |
| 98 | #define RISAB_PG18_C2PRIVCFGR U(0x648) |
| 99 | #define RISAB_PG19_C2PRIVCFGR U(0x64C) |
| 100 | #define RISAB_PG20_C2PRIVCFGR U(0x650) |
| 101 | #define RISAB_PG21_C2PRIVCFGR U(0x654) |
| 102 | #define RISAB_PG22_C2PRIVCFGR U(0x658) |
| 103 | #define RISAB_PG23_C2PRIVCFGR U(0x65C) |
| 104 | #define RISAB_PG24_C2PRIVCFGR U(0x660) |
| 105 | #define RISAB_PG25_C2PRIVCFGR U(0x664) |
| 106 | #define RISAB_PG26_C2PRIVCFGR U(0x668) |
| 107 | #define RISAB_PG27_C2PRIVCFGR U(0x66C) |
| 108 | #define RISAB_PG28_C2PRIVCFGR U(0x670) |
| 109 | #define RISAB_PG29_C2PRIVCFGR U(0x674) |
| 110 | #define RISAB_PG30_C2PRIVCFGR U(0x678) |
| 111 | #define RISAB_PG31_C2PRIVCFGR U(0x67C) |
| 112 | #define RISAB_CID0PRIVCFGR U(0x800) |
| 113 | #define RISAB_CID0RDCFGR U(0x808) |
| 114 | #define RISAB_CID0WRCFGR U(0x810) |
| 115 | #define RISAB_CID1PRIVCFGR U(0x820) |
| 116 | #define RISAB_CID1RDCFGR U(0x828) |
| 117 | #define RISAB_CID1WRCFGR U(0x830) |
| 118 | #define RISAB_CID2PRIVCFGR U(0x840) |
| 119 | #define RISAB_CID2RDCFGR U(0x848) |
| 120 | #define RISAB_CID2WRCFGR U(0x850) |
| 121 | #define RISAB_CID3PRIVCFGR U(0x860) |
| 122 | #define RISAB_CID3RDCFGR U(0x868) |
| 123 | #define RISAB_CID3WRCFGR U(0x870) |
| 124 | #define RISAB_CID4PRIVCFGR U(0x880) |
| 125 | #define RISAB_CID4RDCFGR U(0x888) |
| 126 | #define RISAB_CID4WRCFGR U(0x890) |
| 127 | #define RISAB_CID5PRIVCFGR U(0x8A0) |
| 128 | #define RISAB_CID5RDCFGR U(0x8A8) |
| 129 | #define RISAB_CID5WRCFGR U(0x8B0) |
| 130 | #define RISAB_CID6PRIVCFGR U(0x8C0) |
| 131 | #define RISAB_CID6RDCFGR U(0x8C8) |
| 132 | #define RISAB_CID6WRCFGR U(0x8D0) |
| 133 | #define RISAB_PG0_CIDCFGR U(0xA00) |
| 134 | #define RISAB_PG1_CIDCFGR U(0xA04) |
| 135 | #define RISAB_PG2_CIDCFGR U(0xA08) |
| 136 | #define RISAB_PG3_CIDCFGR U(0xA0C) |
| 137 | #define RISAB_PG4_CIDCFGR U(0xA10) |
| 138 | #define RISAB_PG5_CIDCFGR U(0xA14) |
| 139 | #define RISAB_PG6_CIDCFGR U(0xA18) |
| 140 | #define RISAB_PG7_CIDCFGR U(0xA1C) |
| 141 | #define RISAB_PG8_CIDCFGR U(0xA20) |
| 142 | #define RISAB_PG9_CIDCFGR U(0xA24) |
| 143 | #define RISAB_PG10_CIDCFGR U(0xA28) |
| 144 | #define RISAB_PG11_CIDCFGR U(0xA2C) |
| 145 | #define RISAB_PG12_CIDCFGR U(0xA30) |
| 146 | #define RISAB_PG13_CIDCFGR U(0xA34) |
| 147 | #define RISAB_PG14_CIDCFGR U(0xA38) |
| 148 | #define RISAB_PG15_CIDCFGR U(0xA3C) |
| 149 | #define RISAB_PG16_CIDCFGR U(0xA40) |
| 150 | #define RISAB_PG17_CIDCFGR U(0xA44) |
| 151 | #define RISAB_PG18_CIDCFGR U(0xA48) |
| 152 | #define RISAB_PG19_CIDCFGR U(0xA4C) |
| 153 | #define RISAB_PG20_CIDCFGR U(0xA50) |
| 154 | #define RISAB_PG21_CIDCFGR U(0xA54) |
| 155 | #define RISAB_PG22_CIDCFGR U(0xA58) |
| 156 | #define RISAB_PG23_CIDCFGR U(0xA5C) |
| 157 | #define RISAB_PG24_CIDCFGR U(0xA60) |
| 158 | #define RISAB_PG25_CIDCFGR U(0xA64) |
| 159 | #define RISAB_PG26_CIDCFGR U(0xA68) |
| 160 | #define RISAB_PG27_CIDCFGR U(0xA6C) |
| 161 | #define RISAB_PG28_CIDCFGR U(0xA70) |
| 162 | #define RISAB_PG29_CIDCFGR U(0xA74) |
| 163 | #define RISAB_PG30_CIDCFGR U(0xA78) |
| 164 | #define RISAB_PG31_CIDCFGR U(0xA7C) |
| 165 | #define RISAB_HWCFGR3 U(0xFE8) |
| 166 | #define RISAB_HWCFGR2 U(0xFEC) |
| 167 | #define RISAB_HWCFGR1 U(0xFF0) |
| 168 | #define RISAB_VERR U(0xFF4) |
| 169 | #define RISAB_IPIDR U(0xFF8) |
| 170 | #define RISAB_SIDR U(0xFFC) |
| 171 | |
| 172 | /* RISAB_CR register fields */ |
| 173 | #define RISAB_CR_GLOCK BIT(0) |
| 174 | #define RISAB_CR_SRWIAD BIT(31) |
| 175 | |
| 176 | /* RISAB_IASR register fields */ |
| 177 | #define RISAB_IASR_CAEF BIT(0) |
| 178 | #define RISAB_IASR_IAEF BIT(1) |
| 179 | |
| 180 | /* RISAB_IACR register fields */ |
| 181 | #define RISAB_IACR_CAEF BIT(0) |
| 182 | #define RISAB_IACR_IAEF BIT(1) |
| 183 | |
| 184 | /* RISAB_RIFLOCKR register fields */ |
| 185 | #define RISAB_RIFLOCKR_RLOCK0 BIT(0) |
| 186 | #define RISAB_RIFLOCKR_RLOCK1 BIT(1) |
| 187 | #define RISAB_RIFLOCKR_RLOCK2 BIT(2) |
| 188 | #define RISAB_RIFLOCKR_RLOCK3 BIT(3) |
| 189 | #define RISAB_RIFLOCKR_RLOCK4 BIT(4) |
| 190 | #define RISAB_RIFLOCKR_RLOCK5 BIT(5) |
| 191 | #define RISAB_RIFLOCKR_RLOCK6 BIT(6) |
| 192 | #define RISAB_RIFLOCKR_RLOCK7 BIT(7) |
| 193 | #define RISAB_RIFLOCKR_RLOCK8 BIT(8) |
| 194 | #define RISAB_RIFLOCKR_RLOCK9 BIT(9) |
| 195 | #define RISAB_RIFLOCKR_RLOCK10 BIT(10) |
| 196 | #define RISAB_RIFLOCKR_RLOCK11 BIT(11) |
| 197 | #define RISAB_RIFLOCKR_RLOCK12 BIT(12) |
| 198 | #define RISAB_RIFLOCKR_RLOCK13 BIT(13) |
| 199 | #define RISAB_RIFLOCKR_RLOCK14 BIT(14) |
| 200 | #define RISAB_RIFLOCKR_RLOCK15 BIT(15) |
| 201 | #define RISAB_RIFLOCKR_RLOCK16 BIT(16) |
| 202 | #define RISAB_RIFLOCKR_RLOCK17 BIT(17) |
| 203 | #define RISAB_RIFLOCKR_RLOCK18 BIT(18) |
| 204 | #define RISAB_RIFLOCKR_RLOCK19 BIT(19) |
| 205 | #define RISAB_RIFLOCKR_RLOCK20 BIT(20) |
| 206 | #define RISAB_RIFLOCKR_RLOCK21 BIT(21) |
| 207 | #define RISAB_RIFLOCKR_RLOCK22 BIT(22) |
| 208 | #define RISAB_RIFLOCKR_RLOCK23 BIT(23) |
| 209 | #define RISAB_RIFLOCKR_RLOCK24 BIT(24) |
| 210 | #define RISAB_RIFLOCKR_RLOCK25 BIT(25) |
| 211 | #define RISAB_RIFLOCKR_RLOCK26 BIT(26) |
| 212 | #define RISAB_RIFLOCKR_RLOCK27 BIT(27) |
| 213 | #define RISAB_RIFLOCKR_RLOCK28 BIT(28) |
| 214 | #define RISAB_RIFLOCKR_RLOCK29 BIT(29) |
| 215 | #define RISAB_RIFLOCKR_RLOCK30 BIT(30) |
| 216 | #define RISAB_RIFLOCKR_RLOCK31 BIT(31) |
| 217 | |
| 218 | /* RISAB_IAESR register fields */ |
| 219 | #define RISAB_IAESR_IACID_MASK GENMASK(2, 0) |
| 220 | #define RISAB_IAESR_IACID_SHIFT 0 |
| 221 | #define RISAB_IAESR_IAPRIV BIT(4) |
| 222 | #define RISAB_IAESR_IASEC BIT(5) |
| 223 | #define RISAB_IAESR_IANRW BIT(7) |
| 224 | |
| 225 | /* RISAB_PGx_SECCFGR register fields */ |
| 226 | #define RISAB_PGx_SECCFGR_SEC(_y) BIT(_y) |
| 227 | |
| 228 | /* RISAB_PGx_PRIVCFGR register fields */ |
| 229 | #define RISAB_PGx_PRIVCFGR_PRIV(_y) BIT(_y) |
| 230 | |
| 231 | /* RISAB_PGx_CmPRIVCFGR register fields */ |
| 232 | #define RISAB_PGx_CmPRIVCFGR_PRIV(_y) BIT(_y) |
| 233 | |
| 234 | /* RISAB_CIDxPRIVCFGR register fields */ |
| 235 | #define RISAB_CIDxPRIVCFGR_PPRIV(_y) BIT(_y) |
| 236 | |
| 237 | /* RISAB_CIDxRDCFGR register fields */ |
| 238 | #define RISAB_CIDxRDCFGR_PRDEN(_y) BIT(_y) |
| 239 | |
| 240 | /* RISAB_CIDxWRCFGR register fields */ |
| 241 | #define RISAB_CIDxWRCFGR_PWREN(_y) BIT(_y) |
| 242 | |
| 243 | /* RISAB_PGx_CIDCFGR register fields */ |
| 244 | #define RISAB_PGx_CIDCFGR_CFEN BIT(0) |
| 245 | #define RISAB_PGx_CIDCFGR_DCEN BIT(2) |
| 246 | #define RISAB_PGx_CIDCFGR_DCCID_MASK GENMASK(6, 4) |
| 247 | #define RISAB_PGx_CIDCFGR_DCCID_SHIFT 4 |
| 248 | |
| 249 | /* RISAB_HWCFGR1 register fields */ |
| 250 | #define RISAB_HWCFGR1_CFG1_MASK GENMASK(3, 0) |
| 251 | #define RISAB_HWCFGR1_CFG1_SHIFT 0 |
| 252 | #define RISAB_HWCFGR1_CFG2_MASK GENMASK(7, 4) |
| 253 | #define RISAB_HWCFGR1_CFG2_SHIFT 4 |
| 254 | #define RISAB_HWCFGR1_CFG3_MASK GENMASK(11, 8) |
| 255 | #define RISAB_HWCFGR1_CFG3_SHIFT 8 |
| 256 | #define RISAB_HWCFGR1_CFG4_MASK GENMASK(15, 12) |
| 257 | #define RISAB_HWCFGR1_CFG4_SHIFT 12 |
| 258 | #define RISAB_HWCFGR1_CFG5_MASK GENMASK(19, 16) |
| 259 | #define RISAB_HWCFGR1_CFG5_SHIFT 16 |
| 260 | #define RISAB_HWCFGR1_CFG6_MASK GENMASK(23, 20) |
| 261 | #define RISAB_HWCFGR1_CFG6_SHIFT 20 |
| 262 | #define RISAB_HWCFGR1_CFG7_MASK GENMASK(27, 24) |
| 263 | #define RISAB_HWCFGR1_CFG7_SHIFT 24 |
| 264 | |
| 265 | /* RISAB_VERR register fields */ |
| 266 | #define RISAB_VERR_MINREV_MASK GENMASK(3, 0) |
| 267 | #define RISAB_VERR_MINREV_SHIFT 0 |
| 268 | #define RISAB_VERR_MAJREV_MASK GENMASK(7, 4) |
| 269 | #define RISAB_VERR_MAJREV_SHIFT 4 |
| 270 | |
| 271 | #endif /* STM32MP_RISAB_REGS_H */ |