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David Cunadoce88eee2017-10-20 11:30:57 +01001/*
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +00002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
David Cunadoce88eee2017-10-20 11:30:57 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <pubsub.h>
10#include <sve.h>
11
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000012int sve_supported(void)
David Cunadoce88eee2017-10-20 11:30:57 +010013{
14 uint64_t features;
15
16 features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000017 return (features & ID_AA64PFR0_SVE_MASK) == 1;
18}
David Cunadoce88eee2017-10-20 11:30:57 +010019
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000020static void *disable_sve_hook(const void *arg)
21{
22 uint64_t cptr;
David Cunadoce88eee2017-10-20 11:30:57 +010023
Dimitris Papastamosaaa19852018-02-26 17:56:31 +000024 if (sve_supported() == 0)
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000025 return (void *)-1;
26
27 /*
28 * Disable SVE, SIMD and FP access for the Secure world.
29 * As the SIMD/FP registers are part of the SVE Z-registers, any
30 * use of SIMD/FP functionality will corrupt the SVE registers.
31 * Therefore it is necessary to prevent use of SIMD/FP support
32 * in the Secure world as well as SVE functionality.
33 */
34 cptr = read_cptr_el3();
35 cptr = (cptr | TFP_BIT) & ~(CPTR_EZ_BIT);
36 write_cptr_el3(cptr);
37
38 /*
39 * No explicit ISB required here as ERET to switch to Secure
40 * world covers it
41 */
David Cunadoce88eee2017-10-20 11:30:57 +010042 return 0;
43}
44
45static void *enable_sve_hook(const void *arg)
46{
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000047 uint64_t cptr;
David Cunadoce88eee2017-10-20 11:30:57 +010048
Dimitris Papastamosaaa19852018-02-26 17:56:31 +000049 if (sve_supported() == 0)
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000050 return (void *)-1;
David Cunadoce88eee2017-10-20 11:30:57 +010051
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000052 /*
53 * Enable SVE, SIMD and FP access for the Non-secure world.
54 */
55 cptr = read_cptr_el3();
56 cptr = (cptr | CPTR_EZ_BIT) & ~(TFP_BIT);
57 write_cptr_el3(cptr);
David Cunadoce88eee2017-10-20 11:30:57 +010058
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000059 /*
60 * No explicit ISB required here as ERET to switch to Non-secure
61 * world covers it
62 */
David Cunadoce88eee2017-10-20 11:30:57 +010063 return 0;
64}
65
66void sve_enable(int el2_unused)
67{
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000068 uint64_t cptr;
David Cunadoce88eee2017-10-20 11:30:57 +010069
Dimitris Papastamosaaa19852018-02-26 17:56:31 +000070 if (sve_supported() == 0)
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000071 return;
72
David Cunadoce88eee2017-10-20 11:30:57 +010073#if CTX_INCLUDE_FPREGS
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000074 /*
75 * CTX_INCLUDE_FPREGS is not supported on SVE enabled systems.
76 */
77 assert(0);
David Cunadoce88eee2017-10-20 11:30:57 +010078#endif
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000079 /*
80 * Update CPTR_EL3 to enable access to SVE functionality for the
81 * Non-secure world.
82 * NOTE - assumed that CPTR_EL3.TFP is set to allow access to
83 * the SIMD, floating-point and SVE support.
84 *
85 * CPTR_EL3.EZ: Set to 1 to enable access to SVE functionality
86 * in the Non-secure world.
87 */
88 cptr = read_cptr_el3();
89 cptr |= CPTR_EZ_BIT;
90 write_cptr_el3(cptr);
David Cunadoce88eee2017-10-20 11:30:57 +010091
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000092 /*
93 * Need explicit ISB here to guarantee that update to ZCR_ELx
94 * and CPTR_EL2.TZ do not result in trap to EL3.
95 */
96 isb();
97
98 /*
99 * Ensure lower ELs have access to full vector length.
100 */
101 write_zcr_el3(ZCR_EL3_LEN_MASK);
David Cunadoce88eee2017-10-20 11:30:57 +0100102
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +0000103 if (el2_unused) {
David Cunadoce88eee2017-10-20 11:30:57 +0100104 /*
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +0000105 * Update CPTR_EL2 to enable access to SVE functionality
106 * for Non-secure world, EL2 and Non-secure EL1 and EL0.
107 * NOTE - assumed that CPTR_EL2.TFP is set to allow
108 * access to the SIMD, floating-point and SVE support.
109 *
110 * CPTR_EL2.TZ: Set to 0 to enable access to SVE support
111 * for EL2 and Non-secure EL1 and EL0.
David Cunadoce88eee2017-10-20 11:30:57 +0100112 */
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +0000113 cptr = read_cptr_el2();
114 cptr &= ~(CPTR_EL2_TZ_BIT);
115 write_cptr_el2(cptr);
David Cunadoce88eee2017-10-20 11:30:57 +0100116
David Cunadoce88eee2017-10-20 11:30:57 +0100117 /*
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +0000118 * Ensure lower ELs have access to full vector length.
David Cunadoce88eee2017-10-20 11:30:57 +0100119 */
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +0000120 write_zcr_el2(ZCR_EL2_LEN_MASK);
David Cunadoce88eee2017-10-20 11:30:57 +0100121 }
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +0000122 /*
123 * No explicit ISB required here as ERET to switch to
124 * Non-secure world covers it.
125 */
David Cunadoce88eee2017-10-20 11:30:57 +0100126}
127
128SUBSCRIBE_TO_EVENT(cm_exited_normal_world, disable_sve_hook);
129SUBSCRIBE_TO_EVENT(cm_entering_normal_world, enable_sve_hook);