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Madhukar Pappireddy862c4b82020-02-13 15:36:50 -06001/*
2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9#include "fvp-base-gicv3-psci-common.dtsi"
10
11/* DynamIQ based designs have upto 8 CPUs in each cluster */
12
13&CPU_MAP {
14 cluster0 {
15 core0 {
16 cpu = <&CPU0>;
17 };
18 core1 {
19 cpu = <&CPU1>;
20 };
21 core2 {
22 cpu = <&CPU2>;
23 };
24 core3 {
25 cpu = <&CPU3>;
26 };
27 core4 {
28 cpu = <&CPU4>;
29 };
30 core5 {
31 cpu = <&CPU5>;
32 };
33 core6 {
34 cpu = <&CPU6>;
35 };
36 core7 {
37 cpu = <&CPU7>;
38 };
39 };
40};