Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 1 | /* |
Tintu Thomas | b3ed447 | 2023-02-21 17:51:24 +0000 | [diff] [blame] | 2 | * Copyright (c) 2020-2023, Arm Limited. All rights reserved. |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | #include <lib/xlat_tables/xlat_tables_defs.h> |
| 12 | #include <plat/arm/board/common/board_css_def.h> |
| 13 | #include <plat/arm/board/common/v2m_def.h> |
| 14 | #include <plat/arm/common/arm_def.h> |
| 15 | #include <plat/arm/common/arm_spm_def.h> |
| 16 | #include <plat/arm/css/common/css_def.h> |
| 17 | #include <plat/arm/soc/common/soc_css_def.h> |
| 18 | #include <plat/common/common_def.h> |
| 19 | |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 20 | #define PLATFORM_CORE_COUNT 8 |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 21 | |
| 22 | #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ |
| 23 | |
| 24 | /* |
Arunachalam Ganapathy | 81da558 | 2020-09-22 12:47:33 +0100 | [diff] [blame] | 25 | * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, |
| 26 | * its base is ARM_AP_TZC_DRAM1_BASE. |
| 27 | * |
Arunachalam Ganapathy | ac9e120 | 2022-04-11 17:38:17 +0100 | [diff] [blame] | 28 | * Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for: |
Arunachalam Ganapathy | 81da558 | 2020-09-22 12:47:33 +0100 | [diff] [blame] | 29 | * - BL32_BASE when SPD_spmd is enabled |
Arunachalam Ganapathy | ac9e120 | 2022-04-11 17:38:17 +0100 | [diff] [blame] | 30 | * - Region to load secure partitions |
| 31 | * |
| 32 | * |
| 33 | * 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE |
| 34 | * | | |
| 35 | * | SPMC | |
| 36 | * | SP | |
| 37 | * | (96MB) | |
| 38 | * 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE |
| 39 | * | AP | |
| 40 | * | EL3 Monitor | |
| 41 | * | SCP | |
| 42 | * | (16MB) | |
| 43 | * 0xFFFF_FFFF ------------------ |
| 44 | * |
| 45 | * |
Arunachalam Ganapathy | 81da558 | 2020-09-22 12:47:33 +0100 | [diff] [blame] | 46 | */ |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 47 | #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ |
| 48 | TC_TZC_DRAM1_SIZE) |
Arunachalam Ganapathy | ac9e120 | 2022-04-11 17:38:17 +0100 | [diff] [blame] | 49 | #define TC_TZC_DRAM1_SIZE 96 * SZ_1M /* 96 MB */ |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 50 | #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ |
| 51 | TC_TZC_DRAM1_SIZE - 1) |
Arunachalam Ganapathy | 81da558 | 2020-09-22 12:47:33 +0100 | [diff] [blame] | 52 | |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 53 | #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE |
| 54 | #define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ |
Arunachalam Ganapathy | 81da558 | 2020-09-22 12:47:33 +0100 | [diff] [blame] | 55 | ARM_TZC_DRAM1_SIZE - \ |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 56 | TC_TZC_DRAM1_SIZE) |
| 57 | #define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + \ |
| 58 | TC_NS_DRAM1_SIZE - 1) |
Arunachalam Ganapathy | 81da558 | 2020-09-22 12:47:33 +0100 | [diff] [blame] | 59 | |
| 60 | /* |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 61 | * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) |
Arunachalam Ganapathy | 81da558 | 2020-09-22 12:47:33 +0100 | [diff] [blame] | 62 | */ |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 63 | #define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ |
| 64 | TC_NS_DRAM1_BASE, \ |
| 65 | TC_NS_DRAM1_SIZE, \ |
Arunachalam Ganapathy | 81da558 | 2020-09-22 12:47:33 +0100 | [diff] [blame] | 66 | MT_MEMORY | MT_RW | MT_NS) |
| 67 | |
| 68 | |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 69 | #define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ |
| 70 | TC_TZC_DRAM1_BASE, \ |
| 71 | TC_TZC_DRAM1_SIZE, \ |
Arunachalam Ganapathy | 81da558 | 2020-09-22 12:47:33 +0100 | [diff] [blame] | 72 | MT_MEMORY | MT_RW | MT_SECURE) |
Usama Arif | a49bd49 | 2021-08-17 17:57:10 +0100 | [diff] [blame] | 73 | |
| 74 | #define PLAT_HW_CONFIG_DTB_BASE ULL(0x83000000) |
| 75 | #define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000) |
| 76 | |
| 77 | #define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \ |
| 78 | PLAT_HW_CONFIG_DTB_BASE, \ |
| 79 | PLAT_HW_CONFIG_DTB_SIZE, \ |
| 80 | MT_MEMORY | MT_RO | MT_NS) |
Arunachalam Ganapathy | ade4a20 | 2020-09-22 12:50:45 +0100 | [diff] [blame] | 81 | /* |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 82 | * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to |
Arunachalam Ganapathy | ade4a20 | 2020-09-22 12:50:45 +0100 | [diff] [blame] | 83 | * max size of BL32 image. |
| 84 | */ |
| 85 | #if defined(SPD_spmd) |
Arunachalam Ganapathy | ac9e120 | 2022-04-11 17:38:17 +0100 | [diff] [blame] | 86 | #define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000) |
| 87 | |
| 88 | #define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR |
Arunachalam Ganapathy | ade4a20 | 2020-09-22 12:50:45 +0100 | [diff] [blame] | 89 | #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ |
| 90 | #endif |
Arunachalam Ganapathy | 81da558 | 2020-09-22 12:47:33 +0100 | [diff] [blame] | 91 | |
| 92 | /* |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 93 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 94 | * plat_arm_mmap array defined for each BL stage. |
| 95 | */ |
| 96 | #if defined(IMAGE_BL31) |
| 97 | # if SPM_MM |
| 98 | # define PLAT_ARM_MMAP_ENTRIES 9 |
| 99 | # define MAX_XLAT_TABLES 7 |
| 100 | # define PLAT_SP_IMAGE_MMAP_REGIONS 7 |
| 101 | # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 |
| 102 | # else |
| 103 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 104 | # define MAX_XLAT_TABLES 8 |
| 105 | # endif |
| 106 | #elif defined(IMAGE_BL32) |
| 107 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 108 | # define MAX_XLAT_TABLES 5 |
| 109 | #elif !USE_ROMLIB |
| 110 | # define PLAT_ARM_MMAP_ENTRIES 11 |
| 111 | # define MAX_XLAT_TABLES 7 |
| 112 | #else |
| 113 | # define PLAT_ARM_MMAP_ENTRIES 12 |
| 114 | # define MAX_XLAT_TABLES 6 |
| 115 | #endif |
| 116 | |
| 117 | /* |
| 118 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 119 | * plus a little space for growth. |
| 120 | */ |
Mate Toth-Pal | 14ba4af | 2022-10-21 14:24:49 +0200 | [diff] [blame] | 121 | #define PLAT_ARM_MAX_BL1_RW_SIZE 0x12000 |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 122 | |
| 123 | /* |
| 124 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 125 | */ |
| 126 | |
| 127 | #if USE_ROMLIB |
| 128 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 |
| 129 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 |
| 130 | #else |
| 131 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 |
| 132 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 |
| 133 | #endif |
| 134 | |
| 135 | /* |
| 136 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
David Vincze | aab55dd | 2022-05-04 10:11:16 +0200 | [diff] [blame] | 137 | * little space for growth. Current size is considering that TRUSTED_BOARD_BOOT |
| 138 | * and MEASURED_BOOT is enabled. |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 139 | */ |
David Vincze | aab55dd | 2022-05-04 10:11:16 +0200 | [diff] [blame] | 140 | # define PLAT_ARM_MAX_BL2_SIZE 0x26000 |
| 141 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 142 | |
| 143 | /* |
| 144 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 145 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
David Vincze | aab55dd | 2022-05-04 10:11:16 +0200 | [diff] [blame] | 146 | * BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and |
| 147 | * MEASURED_BOOT is enabled. |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 148 | */ |
Mate Toth-Pal | 14ba4af | 2022-10-21 14:24:49 +0200 | [diff] [blame] | 149 | #define PLAT_ARM_MAX_BL31_SIZE 0x60000 |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 150 | |
| 151 | /* |
| 152 | * Size of cacheable stacks |
| 153 | */ |
| 154 | #if defined(IMAGE_BL1) |
| 155 | # if TRUSTED_BOARD_BOOT |
| 156 | # define PLATFORM_STACK_SIZE 0x1000 |
| 157 | # else |
| 158 | # define PLATFORM_STACK_SIZE 0x440 |
| 159 | # endif |
| 160 | #elif defined(IMAGE_BL2) |
| 161 | # if TRUSTED_BOARD_BOOT |
| 162 | # define PLATFORM_STACK_SIZE 0x1000 |
| 163 | # else |
| 164 | # define PLATFORM_STACK_SIZE 0x400 |
| 165 | # endif |
| 166 | #elif defined(IMAGE_BL2U) |
| 167 | # define PLATFORM_STACK_SIZE 0x400 |
| 168 | #elif defined(IMAGE_BL31) |
| 169 | # if SPM_MM |
| 170 | # define PLATFORM_STACK_SIZE 0x500 |
| 171 | # else |
Mate Toth-Pal | 14ba4af | 2022-10-21 14:24:49 +0200 | [diff] [blame] | 172 | # define PLATFORM_STACK_SIZE 0xa00 |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 173 | # endif |
| 174 | #elif defined(IMAGE_BL32) |
| 175 | # define PLATFORM_STACK_SIZE 0x440 |
| 176 | #endif |
| 177 | |
David Vincze | 0a5a38b | 2022-04-11 17:08:20 +0200 | [diff] [blame] | 178 | /* |
| 179 | * In the current implementation the RoT Service request that requires the |
| 180 | * biggest message buffer is the RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The |
| 181 | * maximum required buffer size is calculated based on the platform-specific |
| 182 | * needs of this request. |
| 183 | */ |
| 184 | #define PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE 0x500 |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 185 | |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 186 | #define TC_DEVICE_BASE 0x21000000 |
| 187 | #define TC_DEVICE_SIZE 0x5f000000 |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 188 | |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 189 | // TC_MAP_DEVICE covers different peripherals |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 190 | // available to the platform |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 191 | #define TC_MAP_DEVICE MAP_REGION_FLAT( \ |
| 192 | TC_DEVICE_BASE, \ |
| 193 | TC_DEVICE_SIZE, \ |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 194 | MT_DEVICE | MT_RW | MT_SECURE) |
| 195 | |
| 196 | |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 197 | #define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 198 | V2M_FLASH0_SIZE, \ |
| 199 | MT_DEVICE | MT_RO | MT_SECURE) |
| 200 | |
| 201 | #define PLAT_ARM_NSTIMER_FRAME_ID 0 |
| 202 | |
Olivier Deprez | 7e5597c | 2022-07-20 17:37:23 +0200 | [diff] [blame] | 203 | #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 |
Olivier Deprez | 7e5597c | 2022-07-20 17:37:23 +0200 | [diff] [blame] | 204 | |
| 205 | /* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ |
| 206 | #define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 207 | |
| 208 | #define PLAT_ARM_NSRAM_BASE 0x06000000 |
| 209 | #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ |
| 210 | |
| 211 | #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) |
| 212 | #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) |
Usama Arif | b496584 | 2021-09-27 18:18:01 +0100 | [diff] [blame] | 213 | #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 214 | |
Madhukar Pappireddy | e108df2 | 2023-03-22 15:40:40 -0500 | [diff] [blame] | 215 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp) |
| 216 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \ |
| 217 | INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \ |
| 218 | GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 219 | GIC_INTR_CFG_LEVEL) |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 220 | |
| 221 | #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ |
| 222 | PLAT_SP_IMAGE_NS_BUF_SIZE) |
| 223 | |
| 224 | /******************************************************************************* |
| 225 | * Memprotect definitions |
| 226 | ******************************************************************************/ |
| 227 | /* PSCI memory protect definitions: |
| 228 | * This variable is stored in a non-secure flash because some ARM reference |
| 229 | * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT |
| 230 | * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. |
| 231 | */ |
| 232 | #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ |
| 233 | V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 234 | |
Madhukar Pappireddy | e108df2 | 2023-03-22 15:40:40 -0500 | [diff] [blame] | 235 | /* Secure Watchdog Constants */ |
| 236 | #define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000) |
| 237 | #define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000) |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 238 | #define SBSA_SECURE_WDOG_TIMEOUT UL(100) |
Madhukar Pappireddy | e108df2 | 2023-03-22 15:40:40 -0500 | [diff] [blame] | 239 | #define SBSA_SECURE_WDOG_INTID 86 |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 240 | |
| 241 | #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 |
| 242 | |
| 243 | #define PLAT_ARM_CLUSTER_COUNT U(1) |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 244 | #define PLAT_MAX_CPUS_PER_CLUSTER U(8) |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 245 | #define PLAT_MAX_PE_PER_CPU U(1) |
| 246 | |
David Vincze | ddab545 | 2022-04-13 14:00:21 +0200 | [diff] [blame] | 247 | /* Message Handling Unit (MHU) base addresses */ |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 248 | #define PLAT_CSS_MHU_BASE UL(0x45400000) |
| 249 | #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE |
| 250 | |
David Vincze | ddab545 | 2022-04-13 14:00:21 +0200 | [diff] [blame] | 251 | /* TC2: AP<->RSS MHUs */ |
| 252 | #define PLAT_RSS_AP_SND_MHU_BASE UL(0x2A840000) |
| 253 | #define PLAT_RSS_AP_RCV_MHU_BASE UL(0x2A850000) |
| 254 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 255 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 |
| 256 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 |
| 257 | |
| 258 | /* |
| 259 | * Physical and virtual address space limits for MMU in AARCH64 |
| 260 | */ |
| 261 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) |
| 262 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) |
| 263 | |
| 264 | /* GIC related constants */ |
| 265 | #define PLAT_ARM_GICD_BASE UL(0x30000000) |
| 266 | #define PLAT_ARM_GICC_BASE UL(0x2C000000) |
Usama Arif | fdfd250 | 2021-03-30 16:39:19 +0100 | [diff] [blame] | 267 | #define PLAT_ARM_GICR_BASE UL(0x30080000) |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 268 | |
| 269 | /* |
| 270 | * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current |
| 271 | * SCP_BL2 size plus a little space for growth. |
| 272 | */ |
Usama Arif | 82d931e | 2020-09-07 18:11:22 +0100 | [diff] [blame] | 273 | #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000 |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 274 | |
| 275 | /* |
| 276 | * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current |
| 277 | * SCP_BL2U size plus a little space for growth. |
| 278 | */ |
Usama Arif | 82d931e | 2020-09-07 18:11:22 +0100 | [diff] [blame] | 279 | #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000 |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 280 | |
Usama Arif | e445ff8 | 2020-08-18 12:30:37 +0100 | [diff] [blame] | 281 | /* TZC Related Constants */ |
| 282 | #define PLAT_ARM_TZC_BASE UL(0x25000000) |
| 283 | #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) |
| 284 | |
| 285 | #define TZC400_OFFSET UL(0x1000000) |
| 286 | #define TZC400_COUNT 4 |
| 287 | |
| 288 | #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ |
| 289 | (n * TZC400_OFFSET)) |
| 290 | |
| 291 | #define TZC_NSAID_DEFAULT U(0) |
| 292 | |
| 293 | #define PLAT_ARM_TZC_NS_DEV_ACCESS \ |
| 294 | (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) |
| 295 | |
Usama Arif | 9bbebe7 | 2020-08-26 14:04:31 +0100 | [diff] [blame] | 296 | /* |
Arunachalam Ganapathy | ac9e120 | 2022-04-11 17:38:17 +0100 | [diff] [blame] | 297 | * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to |
| 298 | * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as |
Usama Arif | b496584 | 2021-09-27 18:18:01 +0100 | [diff] [blame] | 299 | * secure. The second and third regions gives non secure access to rest of DRAM. |
Usama Arif | 9bbebe7 | 2020-08-26 14:04:31 +0100 | [diff] [blame] | 300 | */ |
Usama Arif | b496584 | 2021-09-27 18:18:01 +0100 | [diff] [blame] | 301 | #define TC_TZC_REGIONS_DEF \ |
| 302 | {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ |
| 303 | TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ |
| 304 | {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ |
| 305 | PLAT_ARM_TZC_NS_DEV_ACCESS}, \ |
| 306 | {PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \ |
| 307 | ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} |
Usama Arif | 9bbebe7 | 2020-08-26 14:04:31 +0100 | [diff] [blame] | 308 | |
Arunachalam Ganapathy | ade4a20 | 2020-09-22 12:50:45 +0100 | [diff] [blame] | 309 | /* virtual address used by dynamic mem_protect for chunk_base */ |
| 310 | #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) |
| 311 | |
Tintu Thomas | b3ed447 | 2023-02-21 17:51:24 +0000 | [diff] [blame] | 312 | #if ARM_GPT_SUPPORT |
| 313 | /* |
| 314 | * This overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT in board_css_def.h. |
| 315 | * Offset of the FIP in the GPT image. BL1 component uses this option |
| 316 | * as it does not load the partition table to get the FIP base |
| 317 | * address. At sector 48 for TC to align with ATU page size boundaries (8KiB) |
| 318 | * (i.e. after reserved sectors 0-47). |
| 319 | * Offset = 48 * 512 = 0x6000 |
| 320 | */ |
| 321 | #undef PLAT_ARM_FIP_OFFSET_IN_GPT |
| 322 | #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x6000 |
| 323 | #endif /* ARM_GPT_SUPPORT */ |
| 324 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 325 | #endif /* PLATFORM_DEF_H */ |