Omkar Anand Kulkarni | 1f42599 | 2023-06-22 15:18:07 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <platform_def.h> |
| 8 | #include <sgi_ras.h> |
| 9 | #include <sgi_sdei.h> |
| 10 | |
| 11 | struct sgi_ras_ev_map plat_ras_map[] = { |
| 12 | /* Non Secure base RAM ECC CE interrupt */ |
| 13 | {SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_CE_INT, SGI_RAS_INTR_TYPE_SPI}, |
| 14 | |
| 15 | /* Non Secure base RAM ECC UE interrupt */ |
| 16 | {SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, SGI_RAS_INTR_TYPE_SPI}, |
| 17 | }; |
| 18 | |
| 19 | /* RAS error record list definition, used by the common RAS framework. */ |
| 20 | struct err_record_info plat_err_records[] = { |
| 21 | /* Base element RAM Non-secure error record. */ |
| 22 | ERR_RECORD_MEMMAP_V1(SOC_NS_RAM_ERR_REC_BASE, 4, NULL, |
| 23 | &sgi_ras_sram_intr_handler, 0), |
| 24 | }; |
| 25 | |
| 26 | /* RAS error interrupt list definition, used by the common RAS framework. */ |
| 27 | struct ras_interrupt plat_ras_interrupts[] = { |
| 28 | { |
| 29 | .intr_number = NS_RAM_ECC_CE_INT, |
| 30 | .err_record = &plat_err_records[0], |
| 31 | }, { |
| 32 | .intr_number = NS_RAM_ECC_UE_INT, |
| 33 | .err_record = &plat_err_records[0], |
| 34 | }, |
| 35 | }; |
| 36 | |
| 37 | /* Registers the RAS error record list with common RAS framework. */ |
| 38 | REGISTER_ERR_RECORD_INFO(plat_err_records); |
| 39 | /* Registers the RAS error interrupt info list with common RAS framework. */ |
| 40 | REGISTER_RAS_INTERRUPTS(plat_ras_interrupts); |
| 41 | |
| 42 | /* Platform RAS handling config data definition */ |
| 43 | struct plat_sgi_ras_config ras_config = { |
| 44 | plat_ras_map, |
| 45 | ARRAY_SIZE(plat_ras_map) |
| 46 | }; |