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Boyan Karatotevbdf953c2022-10-25 11:29:04 +01001/*
2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef CORTEX_X3_H
8#define CORTEX_X3_H
9
10#define CORTEX_X3_MIDR U(0x410FD4E0)
11
12/* Cortex-X3 loop count for CVE-2022-23960 mitigation */
Harrison Mutai82dd5ac2022-11-11 14:09:55 +000013#define CORTEX_X3_BHB_LOOP_COUNT U(132)
Boyan Karatotevbdf953c2022-10-25 11:29:04 +010014
15/*******************************************************************************
16 * CPU Extended Control register specific definitions
17 ******************************************************************************/
18#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4
19
20/*******************************************************************************
21 * CPU Power Control register specific definitions
22 ******************************************************************************/
Harrison Mutai82dd5ac2022-11-11 14:09:55 +000023#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
24#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
25#define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4)
26#define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7)
Boyan Karatotevbdf953c2022-10-25 11:29:04 +010027
Boyan Karatotev6559dbd2022-10-03 14:18:28 +010028/*******************************************************************************
29 * CPU Auxiliary Control register 2 specific definitions.
30 ******************************************************************************/
31#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1
32#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
33
Boyan Karatotevbdf953c2022-10-25 11:29:04 +010034#endif /* CORTEX_X3_H */