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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handleybe234f92014-08-04 16:11:15 +010031#include <arch.h>
32#include <assert.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010033#include <cci400.h>
Vikram Kanigiri40d468c2014-12-23 01:00:22 +000034#include <debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010035#include <mmio.h>
Dan Handleybe234f92014-08-04 16:11:15 +010036
37#define MAX_CLUSTERS 2
38
39static unsigned long cci_base_addr;
40static unsigned int cci_cluster_ix_to_iface[MAX_CLUSTERS];
41
42
43void cci_init(unsigned long cci_base,
44 int slave_iface3_cluster_ix,
45 int slave_iface4_cluster_ix)
46{
47 /*
48 * Check the passed arguments are valid. The cluster indices must be
49 * less than MAX_CLUSTERS, not the same as each other and at least one
50 * of them must be refer to a valid cluster index.
51 */
52 assert(cci_base);
53 assert(slave_iface3_cluster_ix < MAX_CLUSTERS);
54 assert(slave_iface4_cluster_ix < MAX_CLUSTERS);
55 assert(slave_iface3_cluster_ix != slave_iface4_cluster_ix);
56 assert((slave_iface3_cluster_ix >= 0) ||
57 (slave_iface3_cluster_ix >= 0));
58
Vikram Kanigiri40d468c2014-12-23 01:00:22 +000059 WARN("Please migrate to common cci driver, This driver will be" \
60 " deprecated in future\n");
61
Dan Handleybe234f92014-08-04 16:11:15 +010062 cci_base_addr = cci_base;
63 if (slave_iface3_cluster_ix >= 0)
64 cci_cluster_ix_to_iface[slave_iface3_cluster_ix] =
65 SLAVE_IFACE3_OFFSET;
66 if (slave_iface4_cluster_ix >= 0)
67 cci_cluster_ix_to_iface[slave_iface4_cluster_ix] =
68 SLAVE_IFACE4_OFFSET;
69}
Achin Gupta4f6ad662013-10-25 09:08:21 +010070
71static inline unsigned long get_slave_iface_base(unsigned long mpidr)
72{
Dan Handleybe234f92014-08-04 16:11:15 +010073 /*
74 * We assume the TF topology code allocates affinity instances
75 * consecutively from zero.
76 * It is a programming error if this is called without initializing
77 * the slave interface to use for this cluster.
78 */
79 unsigned int cluster_id =
80 (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
81
82 assert(cluster_id < MAX_CLUSTERS);
83 assert(cci_cluster_ix_to_iface[cluster_id] != 0);
84
85 return cci_base_addr + cci_cluster_ix_to_iface[cluster_id];
Achin Gupta4f6ad662013-10-25 09:08:21 +010086}
87
Dan Handleybe234f92014-08-04 16:11:15 +010088void cci_enable_cluster_coherency(unsigned long mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010089{
Dan Handleybe234f92014-08-04 16:11:15 +010090 assert(cci_base_addr);
Achin Gupta4f6ad662013-10-25 09:08:21 +010091 /* Enable Snoops and DVM messages */
92 mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG,
93 DVM_EN_BIT | SNOOP_EN_BIT);
94
95 /* Wait for the dust to settle down */
Dan Handleybe234f92014-08-04 16:11:15 +010096 while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT)
Dan Handleya70615f2014-04-09 12:48:25 +010097 ;
Achin Gupta4f6ad662013-10-25 09:08:21 +010098}
99
Dan Handleybe234f92014-08-04 16:11:15 +0100100void cci_disable_cluster_coherency(unsigned long mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100101{
Dan Handleybe234f92014-08-04 16:11:15 +0100102 assert(cci_base_addr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100103 /* Disable Snoops and DVM messages */
104 mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG,
105 ~(DVM_EN_BIT | SNOOP_EN_BIT));
106
107 /* Wait for the dust to settle down */
Dan Handleybe234f92014-08-04 16:11:15 +0100108 while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT)
Dan Handleya70615f2014-04-09 12:48:25 +0100109 ;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100110}
111