Jacky Bai | 07ed02c | 2020-06-03 14:28:45 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2020 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | #ifndef PLATFORM_DEF_H |
| 7 | #define PLATFORM_DEF_H |
| 8 | |
| 9 | #include <lib/utils_def.h> |
| 10 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 11 | |
| 12 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 13 | #define PLATFORM_LINKER_ARCH aarch64 |
| 14 | |
| 15 | #define PLATFORM_STACK_SIZE 0xB00 |
| 16 | #define CACHE_WRITEBACK_GRANULE 64 |
| 17 | |
| 18 | #define PLAT_PRIMARY_CPU U(0x0) |
| 19 | #define PLATFORM_MAX_CPU_PER_CLUSTER U(4) |
| 20 | #define PLATFORM_CLUSTER_COUNT U(1) |
| 21 | #define PLATFORM_CLUSTER0_CORE_COUNT U(4) |
| 22 | #define PLATFORM_CLUSTER1_CORE_COUNT U(0) |
| 23 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) |
| 24 | |
| 25 | #define IMX_PWR_LVL0 MPIDR_AFFLVL0 |
| 26 | #define IMX_PWR_LVL1 MPIDR_AFFLVL1 |
| 27 | #define IMX_PWR_LVL2 MPIDR_AFFLVL2 |
| 28 | |
| 29 | #define PWR_DOMAIN_AT_MAX_LVL U(1) |
| 30 | #define PLAT_MAX_PWR_LVL U(2) |
| 31 | #define PLAT_MAX_OFF_STATE U(4) |
| 32 | #define PLAT_MAX_RET_STATE U(2) |
| 33 | |
| 34 | #define PLAT_WAIT_RET_STATE U(1) |
| 35 | #define PLAT_STOP_OFF_STATE U(3) |
| 36 | |
| 37 | #define BL31_BASE U(0x960000) |
| 38 | #define BL31_LIMIT U(0x980000) |
| 39 | |
| 40 | /* non-secure uboot base */ |
| 41 | #define PLAT_NS_IMAGE_OFFSET U(0x40200000) |
| 42 | |
| 43 | /* GICv3 base address */ |
| 44 | #define PLAT_GICD_BASE U(0x38800000) |
| 45 | #define PLAT_GICR_BASE U(0x38880000) |
| 46 | |
| 47 | #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) |
| 48 | #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) |
| 49 | |
| 50 | #define MAX_XLAT_TABLES 8 |
| 51 | #define MAX_MMAP_REGIONS 16 |
| 52 | |
| 53 | #define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */ |
| 54 | |
| 55 | #define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */ |
| 56 | #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE |
| 57 | #define PLAT_CRASH_UART_CLK_IN_HZ 24000000 |
| 58 | #define IMX_CONSOLE_BAUDRATE 115200 |
| 59 | |
| 60 | #define IMX_AIPSTZ1 U(0x301f0000) |
| 61 | #define IMX_AIPSTZ2 U(0x305f0000) |
| 62 | #define IMX_AIPSTZ3 U(0x309f0000) |
| 63 | #define IMX_AIPSTZ4 U(0x32df0000) |
| 64 | #define IMX_AIPSTZ5 U(0x30df0000) |
| 65 | |
| 66 | #define IMX_AIPS_BASE U(0x30000000) |
| 67 | #define IMX_AIPS_SIZE U(0x3000000) |
| 68 | #define IMX_GPV_BASE U(0x32000000) |
| 69 | #define IMX_GPV_SIZE U(0x800000) |
| 70 | #define IMX_AIPS1_BASE U(0x30200000) |
| 71 | #define IMX_AIPS4_BASE U(0x32c00000) |
| 72 | #define IMX_ANAMIX_BASE U(0x30360000) |
| 73 | #define IMX_CCM_BASE U(0x30380000) |
| 74 | #define IMX_SRC_BASE U(0x30390000) |
| 75 | #define IMX_GPC_BASE U(0x303a0000) |
| 76 | #define IMX_RDC_BASE U(0x303d0000) |
| 77 | #define IMX_CSU_BASE U(0x303e0000) |
| 78 | #define IMX_WDOG_BASE U(0x30280000) |
| 79 | #define IMX_SNVS_BASE U(0x30370000) |
| 80 | #define IMX_NOC_BASE U(0x32700000) |
| 81 | #define IMX_NOC_SIZE U(0x100000) |
| 82 | #define IMX_TZASC_BASE U(0x32F80000) |
| 83 | #define IMX_IOMUX_GPR_BASE U(0x30340000) |
| 84 | #define IMX_CAAM_BASE U(0x30900000) |
| 85 | #define IMX_DDRC_BASE U(0x3d400000) |
| 86 | #define IMX_DDRPHY_BASE U(0x3c000000) |
| 87 | #define IMX_DDR_IPS_BASE U(0x3d000000) |
| 88 | #define IMX_DDR_IPS_SIZE U(0x1800000) |
| 89 | #define IMX_ROM_BASE U(0x0) |
| 90 | |
| 91 | #define IMX_GIC_BASE PLAT_GICD_BASE |
| 92 | #define IMX_GIC_SIZE U(0x200000) |
| 93 | |
| 94 | #define IMX_HSIOMIX_CTL_BASE U(0x32f10000) |
| 95 | #define IMX_HDMI_CTL_BASE U(0x32fc0000) |
| 96 | #define RTX_RESET_CTL0 U(0x20) |
| 97 | #define RTX_CLK_CTL0 U(0x40) |
| 98 | #define RTX_CLK_CTL1 U(0x50) |
| 99 | #define TX_CONTROL0 U(0x200) |
| 100 | #define TX_CONTROL1 U(0x220) |
| 101 | |
| 102 | #define IMX_MEDIAMIX_CTL_BASE U(0x32ec0000) |
| 103 | #define RSTn_CSR U(0x0) |
| 104 | #define CLK_EN_CSR U(0x4) |
| 105 | #define RST_DIV U(0x8) |
| 106 | #define LCDIF_ARCACHE_CTRL U(0x4c) |
| 107 | #define ISI_CACHE_CTRL U(0x50) |
| 108 | |
| 109 | #define WDOG_WSR U(0x2) |
| 110 | #define WDOG_WCR_WDZST BIT(0) |
| 111 | #define WDOG_WCR_WDBG BIT(1) |
| 112 | #define WDOG_WCR_WDE BIT(2) |
| 113 | #define WDOG_WCR_WDT BIT(3) |
| 114 | #define WDOG_WCR_SRS BIT(4) |
| 115 | #define WDOG_WCR_WDA BIT(5) |
| 116 | #define WDOG_WCR_SRE BIT(6) |
| 117 | #define WDOG_WCR_WDW BIT(7) |
| 118 | |
| 119 | #define SRC_A53RCR0 U(0x4) |
| 120 | #define SRC_A53RCR1 U(0x8) |
| 121 | #define SRC_OTG1PHY_SCR U(0x20) |
| 122 | #define SRC_OTG2PHY_SCR U(0x24) |
| 123 | #define SRC_GPR1_OFFSET U(0x74) |
| 124 | |
| 125 | #define SNVS_LPCR U(0x38) |
| 126 | #define SNVS_LPCR_SRTC_ENV BIT(0) |
| 127 | #define SNVS_LPCR_DP_EN BIT(5) |
| 128 | #define SNVS_LPCR_TOP BIT(6) |
| 129 | |
| 130 | #define IOMUXC_GPR10 U(0x28) |
| 131 | #define GPR_TZASC_EN BIT(0) |
| 132 | #define GPR_TZASC_EN_LOCK BIT(16) |
| 133 | |
| 134 | #define ANAMIX_MISC_CTL U(0x124) |
| 135 | #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) |
| 136 | |
| 137 | #define MAX_CSU_NUM U(64) |
| 138 | |
| 139 | #define OCRAM_S_BASE U(0x00180000) |
| 140 | #define OCRAM_S_SIZE U(0x8000) |
| 141 | #define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) |
| 142 | #define SAVED_DRAM_TIMING_BASE OCRAM_S_BASE |
| 143 | |
| 144 | #define COUNTER_FREQUENCY 8000000 /* 8MHz */ |
| 145 | |
| 146 | #define IMX_WDOG_B_RESET |
| 147 | |
| 148 | #define GIC_MAP MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW) |
| 149 | #define AIPS_MAP MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW) /* AIPS map */ |
| 150 | #define OCRAM_S_MAP MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_MEMORY | MT_RW) /* OCRAM_S */ |
| 151 | #define DDRC_MAP MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW) /* DDRMIX */ |
| 152 | #define NOC_MAP MAP_REGION_FLAT(IMX_NOC_BASE, IMX_NOC_SIZE, MT_DEVICE | MT_RW) /* NOC QoS */ |
| 153 | |
| 154 | #endif /* platform_def.h */ |