| Aditya Angadi | e650895 | 2019-07-21 22:13:45 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | #include <sgi_base_platform_def.h> |
| 13 | |
| 14 | #define PLAT_ARM_CLUSTER_COUNT U(16) |
| 15 | #define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1) |
| 16 | #define CSS_SGI_MAX_PE_PER_CPU U(1) |
| 17 | |
| 18 | #define PLAT_CSS_MHU_BASE UL(0x45400000) |
| 19 | #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE |
| 20 | |
| 21 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 |
| 22 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 |
| 23 | |
| 24 | /* |
| 25 | * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes |
| 26 | */ |
| 27 | #ifdef __aarch64__ |
| 28 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42) |
| 29 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42) |
| 30 | #else |
| 31 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 32 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 33 | #endif |
| 34 | |
| 35 | /* GIC related constants */ |
| 36 | #define PLAT_ARM_GICD_BASE UL(0x30000000) |
| 37 | #define PLAT_ARM_GICC_BASE UL(0x2C000000) |
| 38 | #define PLAT_ARM_GICR_BASE UL(0x30140000) |
| 39 | |
| 40 | #endif /* PLATFORM_DEF_H */ |