| Sheetal Tigadoli | 58a9eca | 2019-12-18 20:05:09 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016 - 2020, Broadcom |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PAXB_H |
| 8 | #define PAXB_H |
| 9 | |
| 10 | /* total number of PCIe cores */ |
| 11 | #define NUM_OF_SR_PCIE_CORES 8 |
| 12 | #define NUM_OF_NS3Z_PCIE_CORES 1 |
| 13 | |
| 14 | /* |
| 15 | * List of PCIe core and PAXB wrapper memory power registers |
| 16 | */ |
| 17 | #define PCIE_CORE_BASE 0x40000800 |
| 18 | #define PCIE_CORE_SOFT_RST_CFG_BASE (PCIE_CORE_BASE + 0x40) |
| 19 | #define PCIE_CORE_SOFT_RST 0x1 |
| 20 | #define PCIE_CORE_ISO_CFG_BASE (PCIE_CORE_BASE + 0x54) |
| 21 | #define PCIE_CORE_MEM_ISO 0x2 |
| 22 | #define PCIE_CORE_ISO 0x1 |
| 23 | |
| 24 | #define PCIE_CORE_MEM_PWR_BASE (PCIE_CORE_BASE + 0x58) |
| 25 | #define PCIE_PAXB_MEM_PWR_BASE (PCIE_CORE_BASE + 0x5c) |
| 26 | #define PCIE_CORE_PMI_CFG_BASE (PCIE_CORE_BASE + 0x64) |
| 27 | #define PCIE_CORE_RESERVED_CFG (PCIE_CORE_BASE + 0x6c) |
| 28 | #define PCIE_CORE_MEM_PWR_STATUS_BASE (PCIE_CORE_BASE + 0x74) |
| 29 | #define PCIE_PAXB_MEM_PWR_STATUS_BASE (PCIE_CORE_BASE + 0x78) |
| 30 | #define PCIE_CORE_PWR_OFFSET 0x100 |
| 31 | |
| 32 | #define SR_A0_DEVICE_ID 0xd713 |
| 33 | #define SR_B0_DEVICE_ID 0xd714 |
| 34 | /* TODO: Modify device ID once available */ |
| 35 | #define NS3Z_DEVICE_ID 0xd715 |
| 36 | |
| 37 | /* FIXME: change link speed to GEN3 when it's ready */ |
| 38 | #define GEN1_LINK_SPEED 1 |
| 39 | #define GEN2_LINK_SPEED 2 |
| 40 | #define GEN3_LINK_SPEED 3 |
| 41 | |
| 42 | typedef struct { |
| 43 | uint32_t type; |
| 44 | uint32_t device_id; |
| 45 | uint32_t pipemux_idx; |
| 46 | uint32_t num_cores; |
| 47 | int (*pipemux_init)(void); |
| 48 | int (*phy_init)(void); |
| 49 | int (*core_needs_enable)(unsigned int core_idx); |
| 50 | unsigned int (*get_link_width)(unsigned int core_idx); |
| 51 | unsigned int (*get_link_speed)(void); |
| 52 | } paxb_cfg; |
| 53 | |
| 54 | enum paxb_type { |
| 55 | PAXB_SR, |
| 56 | PAXB_NS3Z, |
| 57 | }; |
| 58 | |
| 59 | extern const paxb_cfg *paxb; |
| 60 | |
| 61 | #ifdef USE_PAXB |
| 62 | void paxb_init(void); |
| 63 | void paxb_rc_cfg_write(unsigned int core_idx, unsigned int where, |
| 64 | uint32_t val); |
| 65 | unsigned int paxb_rc_cfg_read(unsigned int core_idx, unsigned int where); |
| 66 | int pcie_core_needs_enable(unsigned int core_idx); |
| 67 | const paxb_cfg *paxb_get_sr_config(void); |
| 68 | #else |
| 69 | static inline void paxb_init(void) |
| 70 | { |
| 71 | } |
| 72 | #endif |
| 73 | |
| 74 | #endif /* PAXB_H */ |