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git01.mediatek.com / filogic / atf / e622a3d8a5b63199095caf082294a03e31101428 / . / fdts / stm32mp131.dtsi
blob: decd812fa183c105af5c69c226dfc3ca646e0b60 [file] [log] [blame]
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/clock/stm32mp13-clks.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/reset/stm32mp13-resets.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 device_type = "cpu";
21 reg = <0>;
22 clocks = <&rcc CK_MPU>;
23 clock-names = "cpu";
24 nvmem-cells = <&part_number_otp>;
25 nvmem-cell-names = "part_number";
26 };
27 };
28
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]29 clocks {
30 clk_csi: clk-csi {
31 #clock-cells = <0>;
32 compatible = "fixed-clock";
33 clock-frequency = <4000000>;
34 };
35
36 clk_hse: clk-hse {
37 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-frequency = <24000000>;
40 };
41
42 clk_hsi: clk-hsi {
43 #clock-cells = <0>;
44 compatible = "fixed-clock";
45 clock-frequency = <64000000>;
46 };
47
48 clk_lse: clk-lse {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <32768>;
52 };
53
54 clk_lsi: clk-lsi {
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 clock-frequency = <32000>;
58 };
59 };
60
61 intc: interrupt-controller@a0021000 {
62 compatible = "arm,cortex-a7-gic";
63 #interrupt-cells = <3>;
64 interrupt-controller;
65 reg = <0xa0021000 0x1000>,
66 <0xa0022000 0x2000>;
67 };
68
69 psci {
70 compatible = "arm,psci-1.0";
71 method = "smc";
72 };
73
74 soc {
75 compatible = "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 interrupt-parent = <&intc>;
79 ranges;
80
81 usart3: serial@4000f000 {
82 compatible = "st,stm32h7-uart";
83 reg = <0x4000f000 0x400>;
84 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&rcc USART3_K>;
86 resets = <&rcc USART3_R>;
87 status = "disabled";
88 };
89
90 uart4: serial@40010000 {
91 compatible = "st,stm32h7-uart";
92 reg = <0x40010000 0x400>;
93 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&rcc UART4_K>;
95 resets = <&rcc UART4_R>;
96 status = "disabled";
97 };
98
99 uart5: serial@40011000 {
100 compatible = "st,stm32h7-uart";
101 reg = <0x40011000 0x400>;
102 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&rcc UART5_K>;
104 resets = <&rcc UART5_R>;
105 status = "disabled";
106 };
107
108 uart7: serial@40018000 {
109 compatible = "st,stm32h7-uart";
110 reg = <0x40018000 0x400>;
111 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&rcc UART7_K>;
113 resets = <&rcc UART7_R>;
114 status = "disabled";
115 };
116
117 uart8: serial@40019000 {
118 compatible = "st,stm32h7-uart";
119 reg = <0x40019000 0x400>;
120 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&rcc UART8_K>;
122 resets = <&rcc UART8_R>;
123 status = "disabled";
124 };
125
126 usart6: serial@44003000 {
127 compatible = "st,stm32h7-uart";
128 reg = <0x44003000 0x400>;
129 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&rcc USART6_K>;
131 resets = <&rcc USART6_R>;
132 status = "disabled";
133 };
134
135 usbotg_hs: usb-otg@49000000 {
136 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
137 reg = <0x49000000 0x40000>;
138 clocks = <&rcc USBO_K>;
139 clock-names = "otg";
140 resets = <&rcc USBO_R>;
141 reset-names = "dwc2";
142 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
143 g-rx-fifo-size = <512>;
144 g-np-tx-fifo-size = <32>;
145 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
146 dr_mode = "otg";
147 usb33d-supply = <&usb33>;
148 status = "disabled";
149 };
150
151 usart1: serial@4c000000 {
152 compatible = "st,stm32h7-uart";
153 reg = <0x4c000000 0x400>;
154 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&rcc USART1_K>;
156 resets = <&rcc USART1_R>;
157 status = "disabled";
158 };
159
160 usart2: serial@4c001000 {
161 compatible = "st,stm32h7-uart";
162 reg = <0x4c001000 0x400>;
163 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&rcc USART2_K>;
165 resets = <&rcc USART2_R>;
166 status = "disabled";
167 };
168
169 i2c3: i2c@4c004000 {
170 compatible = "st,stm32mp13-i2c";
171 reg = <0x4c004000 0x400>;
172 interrupt-names = "event", "error";
173 interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
174 <&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&rcc I2C3_K>;
176 resets = <&rcc I2C3_R>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 st,syscfg-fmp = <&syscfg 0x4 0x4>;
180 i2c-analog-filter;
181 status = "disabled";
182 };
183
184 i2c4: i2c@4c005000 {
185 compatible = "st,stm32mp13-i2c";
186 reg = <0x4c005000 0x400>;
187 interrupt-names = "event", "error";
188 interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
189 <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&rcc I2C4_K>;
191 resets = <&rcc I2C4_R>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 st,syscfg-fmp = <&syscfg 0x4 0x8>;
195 i2c-analog-filter;
196 status = "disabled";
197 };
198
199 i2c5: i2c@4c006000 {
200 compatible = "st,stm32mp13-i2c";
201 reg = <0x4c006000 0x400>;
202 interrupt-names = "event", "error";
203 interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
204 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&rcc I2C5_K>;
206 resets = <&rcc I2C5_R>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 st,syscfg-fmp = <&syscfg 0x4 0x10>;
210 i2c-analog-filter;
211 status = "disabled";
212 };
213
214 rcc: rcc@50000000 {
215 compatible = "st,stm32mp13-rcc", "syscon";
216 reg = <0x50000000 0x1000>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 #clock-cells = <1>;
220 #reset-cells = <1>;
221 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
222 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
223 secure-interrupt-names = "wakeup";
224 };
225
226 pwr_regulators: pwr@50001000 {
227 compatible = "st,stm32mp1,pwr-reg";
228 reg = <0x50001000 0x10>;
229
230 reg11: reg11 {
231 regulator-name = "reg11";
232 regulator-min-microvolt = <1100000>;
233 regulator-max-microvolt = <1100000>;
234 };
235
236 reg18: reg18 {
237 regulator-name = "reg18";
238 regulator-min-microvolt = <1800000>;
239 regulator-max-microvolt = <1800000>;
240 };
241
242 usb33: usb33 {
243 regulator-name = "usb33";
244 regulator-min-microvolt = <3300000>;
245 regulator-max-microvolt = <3300000>;
246 };
247 };
248
249 exti: interrupt-controller@5000d000 {
250 compatible = "st,stm32mp13-exti", "syscon";
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 reg = <0x5000d000 0x400>;
254 };
255
256 syscfg: syscon@50020000 {
257 compatible = "st,stm32mp157-syscfg", "syscon";
258 reg = <0x50020000 0x400>;
259 clocks = <&rcc SYSCFG>;
260 };
261
262 vrefbuf: vrefbuf@50025000 {
263 compatible = "st,stm32-vrefbuf";
264 reg = <0x50025000 0x8>;
265 regulator-min-microvolt = <1500000>;
266 regulator-max-microvolt = <2500000>;
267 clocks = <&rcc VREF>;
268 status = "disabled";
269 };
270
271 hash: hash@54003000 {
272 compatible = "st,stm32mp13-hash";
273 reg = <0x54003000 0x400>;
274 clocks = <&rcc HASH1>;
275 resets = <&rcc HASH1_R>;
276 status = "disabled";
277 };
278
279 rng: rng@54004000 {
280 compatible = "st,stm32mp13-rng";
281 reg = <0x54004000 0x400>;
282 clocks = <&rcc RNG1_K>;
283 resets = <&rcc RNG1_R>;
284 status = "disabled";
285 };
286
287 fmc: memory-controller@58002000 {
288 #address-cells = <2>;
289 #size-cells = <1>;
290 compatible = "st,stm32mp1-fmc2-ebi";
291 reg = <0x58002000 0x1000>;
292 clocks = <&rcc FMC_K>;
293 resets = <&rcc FMC_R>;
294 status = "disabled";
295
296 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
297 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
298 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
299 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
300 <4 0 0x80000000 0x10000000>; /* NAND */
301
302 nand-controller@4,0 {
303 #address-cells = <1>;
304 #size-cells = <0>;
305 compatible = "st,stm32mp1-fmc2-nfc";
306 reg = <4 0x00000000 0x1000>,
307 <4 0x08010000 0x1000>,
308 <4 0x08020000 0x1000>,
309 <4 0x01000000 0x1000>,
310 <4 0x09010000 0x1000>,
311 <4 0x09020000 0x1000>;
312 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
313 status = "disabled";
314 };
315 };
316
317 qspi: spi@58003000 {
318 compatible = "st,stm32f469-qspi";
319 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
320 reg-names = "qspi", "qspi_mm";
321 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&rcc QSPI_K>;
323 resets = <&rcc QSPI_R>;
324 status = "disabled";
325 };
326
327 sdmmc1: mmc@58005000 {
328 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
329 arm,primecell-periphid = <0x20253180>;
330 reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
331 clocks = <&rcc SDMMC1_K>;
332 clock-names = "apb_pclk";
333 resets = <&rcc SDMMC1_R>;
334 cap-sd-highspeed;
335 cap-mmc-highspeed;
336 max-frequency = <120000000>;
337 status = "disabled";
338 };
339
340 sdmmc2: mmc@58007000 {
341 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
342 arm,primecell-periphid = <0x20253180>;
343 reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
344 clocks = <&rcc SDMMC2_K>;
345 clock-names = "apb_pclk";
346 resets = <&rcc SDMMC2_R>;
347 cap-sd-highspeed;
348 cap-mmc-highspeed;
349 max-frequency = <120000000>;
350 status = "disabled";
351 };
352
353 crc1: crc@58009000 {
354 compatible = "st,stm32f7-crc";
355 reg = <0x58009000 0x400>;
356 clocks = <&rcc CRC1>;
357 };
358
359 usbh_ohci: usbh-ohci@5800c000 {
360 compatible = "generic-ohci";
361 reg = <0x5800c000 0x1000>;
362 clocks = <&rcc USBH>;
363 resets = <&rcc USBH_R>;
364 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
365 status = "disabled";
366 };
367
368 usbh_ehci: usbh-ehci@5800d000 {
369 compatible = "generic-ehci";
370 reg = <0x5800d000 0x1000>;
371 clocks = <&rcc USBH>;
372 resets = <&rcc USBH_R>;
373 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
374 companion = <&usbh_ohci>;
375 status = "disabled";
376 };
377
378 iwdg2: watchdog@5a002000 {
379 compatible = "st,stm32mp1-iwdg";
380 reg = <0x5a002000 0x400>;
381 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
382 clock-names = "pclk", "lsi";
383 status = "disabled";
384 };
385
Nicolas Le Bayon01087912021-01-12 18:18:27 +0100[diff] [blame]386 ddr: ddr@5a003000{
387 compatible = "st,stm32mp13-ddr";
388 reg = <0x5a003000 0x550>, <0x5a004000 0x234>;
389 clocks = <&rcc AXIDCG>,
390 <&rcc DDRC1>,
391 <&rcc DDRPHYC>,
392 <&rcc DDRCAPB>,
393 <&rcc DDRPHYCAPB>;
394 clock-names = "axidcg",
395 "ddrc1",
396 "ddrphyc",
397 "ddrcapb",
398 "ddrphycapb";
399 };
400
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]401 usbphyc: usbphyc@5a006000 {
402 #address-cells = <1>;
403 #size-cells = <0>;
404 #clock-cells = <0>;
405 compatible = "st,stm32mp1-usbphyc";
406 reg = <0x5a006000 0x1000>;
407 clocks = <&rcc USBPHY_K>;
408 resets = <&rcc USBPHY_R>;
409 vdda1v1-supply = <&reg11>;
410 vdda1v8-supply = <&reg18>;
411 status = "disabled";
412
413 usbphyc_port0: usb-phy@0 {
414 #phy-cells = <0>;
415 reg = <0>;
416 };
417
418 usbphyc_port1: usb-phy@1 {
419 #phy-cells = <1>;
420 reg = <1>;
421 };
422 };
423
424 iwdg1: watchdog@5c003000 {
425 compatible = "st,stm32mp1-iwdg";
426 reg = <0x5c003000 0x400>;
427 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
429 clock-names = "pclk", "lsi";
430 status = "disabled";
431 };
432
433 bsec: efuse@5c005000 {
434 compatible = "st,stm32mp15-bsec";
435 reg = <0x5c005000 0x400>;
436 #address-cells = <1>;
437 #size-cells = <1>;
438
439 cfg0_otp: cfg0_otp@0 {
440 reg = <0x0 0x2>;
441 };
442 part_number_otp: part_number_otp@4 {
443 reg = <0x4 0x2>;
444 };
445 monotonic_otp: monotonic_otp@10 {
446 reg = <0x10 0x4>;
447 };
448 nand_otp: cfg9_otp@24 {
449 reg = <0x24 0x4>;
450 };
451 nand2_otp: cfg10_otp@28 {
452 reg = <0x28 0x4>;
453 };
454 uid_otp: uid_otp@34 {
455 reg = <0x34 0xc>;
456 };
457 hw2_otp: hw2_otp@48 {
458 reg = <0x48 0x4>;
459 };
460 ts_cal1: calib@5c {
461 reg = <0x5c 0x2>;
462 };
463 ts_cal2: calib@5e {
464 reg = <0x5e 0x2>;
465 };
466 pkh_otp: pkh_otp@60 {
467 reg = <0x60 0x20>;
468 };
469 mac_addr: mac_addr@e4 {
470 reg = <0xe4 0xc>;
471 st,non-secure-otp;
472 };
473 };
474
475 tamp: tamp@5c00a000 {
476 reg = <0x5c00a000 0x400>;
477 };
478
479 /*
480 * Break node order to solve dependency probe issue between
481 * pinctrl and exti.
482 */
Yann Gautier1bbb09e2022-03-11 14:23:43 +0100[diff] [blame]483 pinctrl: pinctrl@50002000 {
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]484 #address-cells = <1>;
485 #size-cells = <1>;
486 compatible = "st,stm32mp135-pinctrl";
487 ranges = <0 0x50002000 0x8400>;
488 interrupt-parent = <&exti>;
489 st,syscfg = <&exti 0x60 0xff>;
490 pins-are-numbered;
491
492 gpioa: gpio@50002000 {
493 gpio-controller;
494 #gpio-cells = <2>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 reg = <0x0 0x400>;
498 clocks = <&rcc GPIOA>;
499 st,bank-name = "GPIOA";
500 ngpios = <16>;
501 gpio-ranges = <&pinctrl 0 0 16>;
502 };
503
504 gpiob: gpio@50003000 {
505 gpio-controller;
506 #gpio-cells = <2>;
507 interrupt-controller;
508 #interrupt-cells = <2>;
509 reg = <0x1000 0x400>;
510 clocks = <&rcc GPIOB>;
511 st,bank-name = "GPIOB";
512 ngpios = <16>;
513 gpio-ranges = <&pinctrl 0 16 16>;
514 };
515
516 gpioc: gpio@50004000 {
517 gpio-controller;
518 #gpio-cells = <2>;
519 interrupt-controller;
520 #interrupt-cells = <2>;
521 reg = <0x2000 0x400>;
522 clocks = <&rcc GPIOC>;
523 st,bank-name = "GPIOC";
524 ngpios = <16>;
525 gpio-ranges = <&pinctrl 0 32 16>;
526 };
527
528 gpiod: gpio@50005000 {
529 gpio-controller;
530 #gpio-cells = <2>;
531 interrupt-controller;
532 #interrupt-cells = <2>;
533 reg = <0x3000 0x400>;
534 clocks = <&rcc GPIOD>;
535 st,bank-name = "GPIOD";
536 ngpios = <16>;
537 gpio-ranges = <&pinctrl 0 48 16>;
538 };
539
540 gpioe: gpio@50006000 {
541 gpio-controller;
542 #gpio-cells = <2>;
543 interrupt-controller;
544 #interrupt-cells = <2>;
545 reg = <0x4000 0x400>;
546 clocks = <&rcc GPIOE>;
547 st,bank-name = "GPIOE";
548 ngpios = <16>;
549 gpio-ranges = <&pinctrl 0 64 16>;
550 };
551
552 gpiof: gpio@50007000 {
553 gpio-controller;
554 #gpio-cells = <2>;
555 interrupt-controller;
556 #interrupt-cells = <2>;
557 reg = <0x5000 0x400>;
558 clocks = <&rcc GPIOF>;
559 st,bank-name = "GPIOF";
560 ngpios = <16>;
561 gpio-ranges = <&pinctrl 0 80 16>;
562 };
563
564 gpiog: gpio@50008000 {
565 gpio-controller;
566 #gpio-cells = <2>;
567 interrupt-controller;
568 #interrupt-cells = <2>;
569 reg = <0x6000 0x400>;
570 clocks = <&rcc GPIOG>;
571 st,bank-name = "GPIOG";
572 ngpios = <16>;
573 gpio-ranges = <&pinctrl 0 96 16>;
574 };
575
576 gpioh: gpio@50009000 {
577 gpio-controller;
578 #gpio-cells = <2>;
579 interrupt-controller;
580 #interrupt-cells = <2>;
581 reg = <0x7000 0x400>;
582 clocks = <&rcc GPIOH>;
583 st,bank-name = "GPIOH";
584 ngpios = <15>;
585 gpio-ranges = <&pinctrl 0 112 15>;
586 };
587
588 gpioi: gpio@5000a000 {
589 gpio-controller;
590 #gpio-cells = <2>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
593 reg = <0x8000 0x400>;
594 clocks = <&rcc GPIOI>;
595 st,bank-name = "GPIOI";
596 ngpios = <8>;
597 gpio-ranges = <&pinctrl 0 128 8>;
598 };
599 };
600 };
601};