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Haojian Zhuang20cd3232017-05-31 11:00:15 +08001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef UFS_H
8#define UFS_H
Haojian Zhuang20cd3232017-05-31 11:00:15 +08009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
fengbaopeng44070ef2018-02-12 20:53:54 +080011
Haojian Zhuang20cd3232017-05-31 11:00:15 +080012/* register map of UFSHCI */
13/* Controller Capabilities */
14#define CAP 0x00
15#define CAP_NUTRS_MASK 0x1F
16
17/* UFS Version */
18#define VER 0x08
19/* Host Controller Identification - Product ID */
20#define HCDDID 0x10
21/* Host Controller Identification Descriptor - Manufacturer ID */
22#define HCPMID 0x14
23/* Auto-Hibernate Idle Timer */
24#define AHIT 0x18
25/* Interrupt Status */
26#define IS 0x20
27/* Interrupt Enable */
28#define IE 0x24
29/* System Bus Fatal Error Status */
30#define UFS_INT_SBFES (1 << 17)
31/* Host Controller Fatal Error Status */
32#define UFS_INT_HCFES (1 << 16)
33/* UTP Error Status */
34#define UFS_INT_UTPES (1 << 12)
35/* Device Fatal Error Status */
36#define UFS_INT_DFES (1 << 11)
37/* UIC Command Completion Status */
38#define UFS_INT_UCCS (1 << 10)
39/* UTP Task Management Request Completion Status */
40#define UFS_INT_UTMRCS (1 << 9)
41/* UIC Link Startup Status */
42#define UFS_INT_ULSS (1 << 8)
43/* UIC Link Lost Status */
44#define UFS_INT_ULLS (1 << 7)
45/* UIC Hibernate Enter Status */
46#define UFS_INT_UHES (1 << 6)
47/* UIC Hibernate Exit Status */
48#define UFS_INT_UHXS (1 << 5)
49/* UIC Power Mode Status */
50#define UFS_INT_UPMS (1 << 4)
51/* UIC Test Mode Status */
52#define UFS_INT_UTMS (1 << 3)
53/* UIC Error */
54#define UFS_INT_UE (1 << 2)
55/* UIC DME_ENDPOINTRESET Indication */
56#define UFS_INT_UDEPRI (1 << 1)
57/* UTP Transfer Request Completion Status */
58#define UFS_INT_UTRCS (1 << 0)
59
60/* Host Controller Status */
61#define HCS 0x30
62#define HCS_UPMCRS_MASK (7 << 8)
63#define HCS_PWR_LOCAL (1 << 8)
64#define HCS_UCRDY (1 << 3)
65#define HCS_UTMRLRDY (1 << 2)
66#define HCS_UTRLRDY (1 << 1)
67#define HCS_DP (1 << 0)
68
69/* Host Controller Enable */
70#define HCE 0x34
71#define HCE_ENABLE 1
anansa93159e2022-03-21 09:59:18 +053072#define HCE_DISABLE 0
Haojian Zhuang20cd3232017-05-31 11:00:15 +080073
74/* Host UIC Error Code PHY Adapter Layer */
75#define UECPA 0x38
76/* Host UIC Error Code Data Link Layer */
77#define UECDL 0x3C
78/* Host UIC Error Code Network Layer */
79#define UECN 0x40
80/* Host UIC Error Code Transport Layer */
81#define UECT 0x44
82/* Host UIC Error Code */
83#define UECDME 0x48
84/* UTP Transfer Request Interrupt Aggregation Control Register */
85#define UTRIACR 0x4C
Justin Chadwell82946022019-07-03 14:15:22 +010086#define UTRIACR_IAEN (1U << 31)
Haojian Zhuang20cd3232017-05-31 11:00:15 +080087#define UTRIACR_IAPWEN (1 << 24)
88#define UTRIACR_IASB (1 << 20)
89#define UTRIACR_CTR (1 << 16)
90#define UTRIACR_IACTH(x) (((x) & 0x1F) << 8)
91#define UTRIACR_IATOVAL(x) ((x) & 0xFF)
92
93/* UTP Transfer Request List Base Address */
94#define UTRLBA 0x50
95/* UTP Transfer Request List Base Address Upper 32-bits */
96#define UTRLBAU 0x54
97/* UTP Transfer Request List Door Bell Register */
98#define UTRLDBR 0x58
99/* UTP Transfer Request List Clear Register */
100#define UTRLCLR 0x5C
101/* UTP Transfer Request List Run Stop Register */
102#define UTRLRSR 0x60
103#define UTMRLBA 0x70
104#define UTMRLBAU 0x74
105#define UTMRLDBR 0x78
106#define UTMRLCLR 0x7C
107#define UTMRLRSR 0x80
108/* UIC Command */
109#define UICCMD 0x90
110/* UIC Command Argument 1 */
111#define UCMDARG1 0x94
112/* UIC Command Argument 2 */
113#define UCMDARG2 0x98
114/* UIC Command Argument 3 */
115#define UCMDARG3 0x9C
116
117#define UFS_BLOCK_SHIFT 12 /* 4KB */
118#define UFS_BLOCK_SIZE (1 << UFS_BLOCK_SHIFT)
119#define UFS_BLOCK_MASK (UFS_BLOCK_SIZE - 1)
120#define UFS_MAX_LUNS 8
121
122/* UTP Transfer Request Descriptor */
123/* Command Type */
124#define CT_UFS_STORAGE 1
125#define CT_SCSI 0
126
127/* Data Direction */
128#define DD_OUT 2 /* Device --> Host */
129#define DD_IN 1 /* Host --> Device */
130#define DD_NO_DATA_TRANSFER 0
131
132#define UTP_TRD_SIZE 32
133
134/* Transaction Type */
135#define TRANS_TYPE_HD (1 << 7) /* E2ECRC */
136#define TRANS_TYPE_DD (1 << 6)
137#define TRANS_TYPE_CODE_MASK 0x3F
138#define QUERY_RESPONSE_UPIU (0x36 << 0)
139#define READY_TO_TRANSACTION_UPIU (0x31 << 0)
140#define DATA_IN_UPIU (0x22 << 0)
141#define RESPONSE_UPIU (0x21 << 0)
142#define NOP_IN_UPIU (0x20 << 0)
143#define QUERY_REQUEST_UPIU (0x16 << 0)
144#define DATA_OUT_UPIU (0x02 << 0)
145#define CMD_UPIU (0x01 << 0)
146#define NOP_OUT_UPIU (0x00 << 0)
147
148#define OCS_SUCCESS 0x0
149#define OCS_INVALID_FUNC_ATTRIBUTE 0x1
150#define OCS_MISMATCH_REQUEST_SIZE 0x2
151#define OCS_MISMATCH_RESPONSE_SIZE 0x3
152#define OCS_PEER_COMMUNICATION_FAILURE 0x4
153#define OCS_ABORTED 0x5
154#define OCS_FATAL_ERROR 0x6
155#define OCS_MASK 0xF
156
157/* UIC Command */
158#define DME_GET 0x01
159#define DME_SET 0x02
160#define DME_PEER_GET 0x03
161#define DME_PEER_SET 0x04
162#define DME_POWERON 0x10
163#define DME_POWEROFF 0x11
164#define DME_ENABLE 0x12
165#define DME_RESET 0x14
166#define DME_ENDPOINTRESET 0x15
167#define DME_LINKSTARTUP 0x16
168#define DME_HIBERNATE_ENTER 0x17
169#define DME_HIBERNATE_EXIT 0x18
170#define DME_TEST_MODE 0x1A
171
172#define GEN_SELECTOR_IDX(x) ((x) & 0xFFFF)
173
174#define CONFIG_RESULT_CODE_MASK 0xFF
175
176#define CDBCMD_TEST_UNIT_READY 0x00
177#define CDBCMD_READ_6 0x08
178#define CDBCMD_WRITE_6 0x0A
179#define CDBCMD_START_STOP_UNIT 0x1B
180#define CDBCMD_READ_CAPACITY_10 0x25
181#define CDBCMD_READ_10 0x28
182#define CDBCMD_WRITE_10 0x2A
183#define CDBCMD_READ_16 0x88
184#define CDBCMD_WRITE_16 0x8A
185#define CDBCMD_READ_CAPACITY_16 0x9E
186#define CDBCMD_REPORT_LUNS 0xA0
187
188#define UPIU_FLAGS_R (1 << 6)
189#define UPIU_FLAGS_W (1 << 5)
190#define UPIU_FLAGS_ATTR_MASK (3 << 0)
191#define UPIU_FLAGS_ATTR_S (0 << 0) /* Simple */
192#define UPIU_FLAGS_ATTR_O (1 << 0) /* Ordered */
193#define UPIU_FLAGS_ATTR_HQ (2 << 0) /* Head of Queue */
194#define UPIU_FLAGS_ATTR_ACA (3 << 0)
195#define UPIU_FLAGS_O (1 << 6)
196#define UPIU_FLAGS_U (1 << 5)
197#define UPIU_FLAGS_D (1 << 4)
198
199#define QUERY_FUNC_STD_READ 0x01
200#define QUERY_FUNC_STD_WRITE 0x81
201
202#define QUERY_NOP 0x00
203#define QUERY_READ_DESC 0x01
204#define QUERY_WRITE_DESC 0x02
205#define QUERY_READ_ATTR 0x03
206#define QUERY_WRITE_ATTR 0x04
207#define QUERY_READ_FLAG 0x05
208#define QUERY_SET_FLAG 0x06
209#define QUERY_CLEAR_FLAG 0x07
210#define QUERY_TOGGLE_FLAG 0x08
211
212#define RW_WITHOUT_CACHE 0x18
213
214#define DESC_TYPE_DEVICE 0x00
215#define DESC_TYPE_CONFIGURATION 0x01
216#define DESC_TYPE_UNIT 0x02
217#define DESC_TYPE_INTERCONNECT 0x04
218#define DESC_TYPE_STRING 0x05
219
fengbaopeng44070ef2018-02-12 20:53:54 +0800220#define DESC_DEVICE_MAX_SIZE 0x1F
221#define DEVICE_DESC_PARAM_MANF_ID 0x18
222
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800223#define ATTR_CUR_PWR_MODE 0x02 /* bCurrentPowerMode */
224#define ATTR_ACTIVECC 0x03 /* bActiveICCLevel */
225
226#define DEVICE_DESCRIPTOR_LEN 0x40
227#define UNIT_DESCRIPTOR_LEN 0x23
228
229#define QUERY_RESP_SUCCESS 0x00
230#define QUERY_RESP_OPCODE 0xFE
231#define QUERY_RESP_GENERAL_FAIL 0xFF
232
233#define SENSE_KEY_NO_SENSE 0x00
234#define SENSE_KEY_RECOVERED_ERROR 0x01
235#define SENSE_KEY_NOT_READY 0x02
236#define SENSE_KEY_MEDIUM_ERROR 0x03
237#define SENSE_KEY_HARDWARE_ERROR 0x04
238#define SENSE_KEY_ILLEGAL_REQUEST 0x05
239#define SENSE_KEY_UNIT_ATTENTION 0x06
240#define SENSE_KEY_DATA_PROTECT 0x07
241#define SENSE_KEY_BLANK_CHECK 0x08
242#define SENSE_KEY_VENDOR_SPECIFIC 0x09
243#define SENSE_KEY_COPY_ABORTED 0x0A
244#define SENSE_KEY_ABORTED_COMMAND 0x0B
245#define SENSE_KEY_VOLUME_OVERFLOW 0x0D
246#define SENSE_KEY_MISCOMPARE 0x0E
247
248#define SENSE_DATA_VALID 0x70
249#define SENSE_DATA_LENGTH 18
250
251#define READ_CAPACITY_LENGTH 8
252
253#define FLAG_DEVICE_INIT 0x01
254
fengbaopeng44070ef2018-02-12 20:53:54 +0800255#define UFS_VENDOR_SKHYNIX U(0x1AD)
256
257#define MAX_MODEL_LEN 16
Jorge Troncoso453e5e72021-09-23 17:14:29 -0700258
259/* maximum number of retries for a general UIC command */
260#define UFS_UIC_COMMAND_RETRIES 3
261
Anand Saminathanae9e92b2022-09-28 02:37:28 +0000262/* maximum number of retries for a transfer command */
263#define UFS_CMD_RETRIES 3
264
Rohit Nerd6f85082022-07-02 04:52:40 -0700265/* maximum number of retries for reading UFS capacity */
266#define UFS_READ_CAPACITY_RETRIES 10
267
Jorge Troncoso63d7c162021-10-05 22:46:35 -0700268/* maximum number of link-startup retries */
269#define DME_LINKSTARTUP_RETRIES 10
270
Jorge Troncoso5f449162021-09-30 16:29:32 -0700271#define HCE_ENABLE_OUTER_RETRIES 3
272#define HCE_ENABLE_INNER_RETRIES 50
273#define HCE_ENABLE_TIMEOUT_US 100
anansa93159e2022-03-21 09:59:18 +0530274#define HCE_DISABLE_TIMEOUT_US 1000
Jorge Troncoso5f449162021-09-30 16:29:32 -0700275
anans44756ec2022-03-21 09:43:11 +0530276#define FDEVICEINIT_TIMEOUT_MS 1500
277
fengbaopeng44070ef2018-02-12 20:53:54 +0800278/**
279 * ufs_dev_desc - ufs device details from the device descriptor
280 * @wmanufacturerid: card details
281 * @model: card model
282 */
283struct ufs_dev_desc {
284 uint16_t wmanufacturerid;
285 int8_t model[MAX_MODEL_LEN + 1];
286};
287
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800288/* UFS Driver Flags */
289#define UFS_FLAGS_SKIPINIT (1 << 0)
fengbaopeng44070ef2018-02-12 20:53:54 +0800290#define UFS_FLAGS_VENDOR_SKHYNIX (U(1) << 2)
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800291
292typedef struct sense_data {
293 uint8_t resp_code : 7;
294 uint8_t valid : 1;
295 uint8_t reserved0;
296 uint8_t sense_key : 4;
297 uint8_t reserved1 : 1;
298 uint8_t ili : 1;
299 uint8_t eom : 1;
300 uint8_t file_mark : 1;
301 uint8_t info[4];
302 uint8_t asl;
303 uint8_t cmd_spec_len[4];
304 uint8_t asc;
305 uint8_t ascq;
306 uint8_t fruc;
307 uint8_t sense_key_spec0 : 7;
308 uint8_t sksv : 1;
309 uint8_t sense_key_spec1;
310 uint8_t sense_key_spec2;
311} sense_data_t;
312
313/* UTP Transfer Request Descriptor */
314typedef struct utrd_header {
315 uint32_t reserved0 : 24;
316 uint32_t i : 1; /* interrupt */
317 uint32_t dd : 2; /* data direction */
318 uint32_t reserved1 : 1;
319 uint32_t ct : 4; /* command type */
320 uint32_t reserved2;
321 uint32_t ocs : 8; /* Overall Command Status */
322 uint32_t reserved3 : 24;
323 uint32_t reserved4;
324 uint32_t ucdba; /* aligned to 128-byte */
325 uint32_t ucdbau; /* Upper 32-bits */
326 uint32_t rul : 16; /* Response UPIU Length */
327 uint32_t ruo : 16; /* Response UPIU Offset */
328 uint32_t prdtl : 16; /* PRDT Length */
329 uint32_t prdto : 16; /* PRDT Offset */
330} utrd_header_t; /* 8 words with little endian */
331
332/* UTP Task Management Request Descriptor */
333typedef struct utp_utmrd {
334 /* 4 words with little endian */
335 uint32_t reserved0 : 24;
336 uint32_t i : 1; /* interrupt */
337 uint32_t reserved1 : 7;
338 uint32_t reserved2;
339 uint32_t ocs : 8; /* Overall Command Status */
340 uint32_t reserved3 : 24;
341 uint32_t reserved4;
342
343 /* followed by 8 words UPIU with big endian */
344
345 /* followed by 8 words Response UPIU with big endian */
346} utp_utmrd_t;
347
348/* NOP OUT UPIU */
349typedef struct nop_out_upiu {
350 uint8_t trans_type;
351 uint8_t flags;
352 uint8_t reserved0;
353 uint8_t task_tag;
354 uint8_t reserved1;
355 uint8_t reserved2;
356 uint8_t reserved3;
357 uint8_t reserved4;
358 uint8_t total_ehs_len;
359 uint8_t reserved5;
360 uint16_t data_segment_len;
361 uint32_t reserved6;
362 uint32_t reserved7;
363 uint32_t reserved8;
364 uint32_t reserved9;
365 uint32_t reserved10;
366 uint32_t e2ecrc;
367} nop_out_upiu_t; /* 36 bytes with big endian */
368
369/* NOP IN UPIU */
370typedef struct nop_in_upiu {
371 uint8_t trans_type;
372 uint8_t flags;
373 uint8_t reserved0;
374 uint8_t task_tag;
375 uint8_t reserved1;
376 uint8_t reserved2;
377 uint8_t response;
378 uint8_t reserved3;
379 uint8_t total_ehs_len;
380 uint8_t dev_info;
381 uint16_t data_segment_len;
382 uint32_t reserved4;
383 uint32_t reserved5;
384 uint32_t reserved6;
385 uint32_t reserved7;
386 uint32_t reserved8;
387 uint32_t e2ecrc;
388} nop_in_upiu_t; /* 36 bytes with big endian */
389
390/* Command UPIU */
391typedef struct cmd_upiu {
392 uint8_t trans_type;
393 uint8_t flags;
394 uint8_t lun;
395 uint8_t task_tag;
396 uint8_t cmd_set_type;
397 uint8_t reserved0;
398 uint8_t reserved1;
399 uint8_t reserved2;
400 uint8_t total_ehs_len;
401 uint8_t reserved3;
402 uint16_t data_segment_len;
403 uint32_t exp_data_trans_len;
404 /*
405 * A CDB has a fixed length of 16bytes or a variable length
406 * of between 12 and 260 bytes
407 */
408 uint8_t cdb[16]; /* little endian */
409} cmd_upiu_t; /* 32 bytes with big endian except for cdb[] */
410
411typedef struct query_desc {
412 uint8_t opcode;
413 uint8_t idn;
414 uint8_t index;
415 uint8_t selector;
416 uint8_t reserved0[2];
417 uint16_t length;
418 uint32_t reserved2[2];
419} query_desc_t; /* 16 bytes with big endian */
420
421typedef struct query_flag {
422 uint8_t opcode;
423 uint8_t idn;
424 uint8_t index;
425 uint8_t selector;
426 uint8_t reserved0[7];
427 uint8_t value;
428 uint32_t reserved8;
429} query_flag_t; /* 16 bytes with big endian */
430
431typedef struct query_attr {
432 uint8_t opcode;
433 uint8_t idn;
434 uint8_t index;
435 uint8_t selector;
436 uint8_t reserved0[4];
437 uint32_t value; /* little endian */
438 uint32_t reserved4;
439} query_attr_t; /* 16 bytes with big endian except for value */
440
441/* Query Request UPIU */
442typedef struct query_upiu {
443 uint8_t trans_type;
444 uint8_t flags;
445 uint8_t reserved0;
446 uint8_t task_tag;
447 uint8_t reserved1;
448 uint8_t query_func;
449 uint8_t reserved2;
450 uint8_t reserved3;
451 uint8_t total_ehs_len;
452 uint8_t reserved4;
453 uint16_t data_segment_len;
454 /* Transaction Specific Fields */
455 union {
456 query_desc_t desc;
457 query_flag_t flag;
458 query_attr_t attr;
459 } ts;
460 uint32_t reserved5;
461} query_upiu_t; /* 32 bytes with big endian */
462
463/* Query Response UPIU */
464typedef struct query_resp_upiu {
465 uint8_t trans_type;
466 uint8_t flags;
467 uint8_t reserved0;
468 uint8_t task_tag;
469 uint8_t reserved1;
470 uint8_t query_func;
471 uint8_t query_resp;
472 uint8_t reserved2;
473 uint8_t total_ehs_len;
474 uint8_t dev_info;
475 uint16_t data_segment_len;
476 union {
477 query_desc_t desc;
478 query_flag_t flag;
479 query_attr_t attr;
480 } ts;
481 uint32_t reserved3;
482} query_resp_upiu_t; /* 32 bytes with big endian */
483
484/* Response UPIU */
485typedef struct resp_upiu {
486 uint8_t trans_type;
487 uint8_t flags;
488 uint8_t lun;
489 uint8_t task_tag;
490 uint8_t cmd_set_type;
491 uint8_t reserved0;
492 uint8_t reserved1;
493 uint8_t status;
494 uint8_t total_ehs_len;
495 uint8_t dev_info;
496 uint16_t data_segment_len;
497 uint32_t res_trans_cnt; /* Residual Transfer Count */
498 uint32_t reserved2[4];
499 uint16_t sense_data_len;
500 union {
501 uint8_t sense_data[18];
502 sense_data_t sense;
503 } sd;
504} resp_upiu_t; /* 52 bytes with big endian */
505
506typedef struct cmd_info {
507 uintptr_t buf;
508 size_t length;
509 int lba;
510 uint8_t op;
511 uint8_t direction;
512 uint8_t lun;
513} cmd_info_t;
514
515typedef struct utp_utrd {
516 uintptr_t header; /* utrd_header_t */
517 uintptr_t upiu;
518 uintptr_t resp_upiu;
519 uintptr_t prdt;
520 size_t size_upiu;
521 size_t size_resp_upiu;
Jorge Troncosof23aedb2023-02-22 15:30:47 -0800522 size_t prdt_length;
Haojian Zhuang20cd3232017-05-31 11:00:15 +0800523 int task_tag;
524} utp_utrd_t;
525
526/* Physical Region Description Table */
527typedef struct prdt {
528 uint32_t dba; /* Data Base Address */
529 uint32_t dbau; /* Data Base Address Upper 32-bits */
530 uint32_t reserved0;
531 uint32_t dbc : 18; /* Data Byte Count */
532 uint32_t reserved1 : 14;
533} prdt_t;
534
535typedef struct uic_cmd {
536 uint32_t op;
537 uint32_t arg1;
538 uint32_t arg2;
539 uint32_t arg3;
540} uic_cmd_t;
541
542typedef struct ufs_params {
543 uintptr_t reg_base;
544 uintptr_t desc_base;
545 size_t desc_size;
546 unsigned long flags;
547} ufs_params_t;
548
549typedef struct ufs_ops {
550 int (*phy_init)(ufs_params_t *params);
551 int (*phy_set_pwr_mode)(ufs_params_t *params);
552} ufs_ops_t;
553
554int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd);
555int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val);
556int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val);
557
558unsigned int ufs_read_attr(int idn);
559void ufs_write_attr(int idn, unsigned int value);
560unsigned int ufs_read_flag(int idn);
561void ufs_set_flag(int idn);
562void ufs_clear_flag(int idn);
563void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size);
564void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size);
565size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size);
566size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size);
567int ufs_init(const ufs_ops_t *ops, ufs_params_t *params);
568
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000569#endif /* UFS_H */