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Antonio Nino Diazae6779e2017-11-06 14:49:04 +00001/*
Andre Przywara4ea3bd32019-07-09 14:32:11 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz9abd78d2018-07-11 21:00:32 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <arch_helpers.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <bl31/interrupt_mgmt.h>
15#include <drivers/console.h>
16#include <drivers/ti/uart/uart_16550.h>
17#include <lib/xlat_tables/xlat_tables_v2.h>
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000018
Andre Przywarabb6ef152019-07-09 11:44:14 +010019#include <rpi_hw.h>
Andre Przywara4ea3bd32019-07-09 14:32:11 +010020#include <rpi_shared.h>
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000021
22#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
23 DEVICE0_SIZE, \
24 MT_DEVICE | MT_RW | MT_SECURE)
25
Andre Przywara0467ce92019-07-15 08:58:23 +010026#ifdef SHARED_RAM_BASE
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000027#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \
28 SHARED_RAM_SIZE, \
Antonio Nino Diazf96582a2018-10-19 00:57:16 +010029 MT_DEVICE | MT_RW | MT_SECURE)
Andre Przywara0467ce92019-07-15 08:58:23 +010030#endif
Antonio Nino Diazf96582a2018-10-19 00:57:16 +010031
32#ifdef RPI3_PRELOADED_DTB_BASE
33#define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \
34 MT_MEMORY | MT_RW | MT_NS)
35#endif
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000036
37#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \
38 MT_MEMORY | MT_RW | MT_NS)
39
40#define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \
41 PLAT_RPI3_FIP_MAX_SIZE, \
42 MT_MEMORY | MT_RO | MT_NS)
43
44#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \
45 MT_MEMORY | MT_RW | MT_SECURE)
46
Ying-Chun Liu (PaulLiu)d9f76e62018-06-10 02:00:27 +080047#ifdef SPD_opteed
48#define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \
49 RPI3_OPTEE_PAGEABLE_LOAD_BASE, \
50 RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \
51 MT_MEMORY | MT_RW | MT_SECURE)
52#endif
53
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000054/*
55 * Table of regions for various BL stages to map using the MMU.
56 */
57#ifdef IMAGE_BL1
58static const mmap_region_t plat_rpi3_mmap[] = {
Andre Przywara0467ce92019-07-15 08:58:23 +010059#ifdef MAP_SHARED_RAM
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000060 MAP_SHARED_RAM,
Andre Przywara0467ce92019-07-15 08:58:23 +010061#endif
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000062 MAP_DEVICE0,
63 MAP_FIP,
Ying-Chun Liu (PaulLiu)d9f76e62018-06-10 02:00:27 +080064#ifdef SPD_opteed
65 MAP_OPTEE_PAGEABLE,
66#endif
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000067 {0}
68};
69#endif
70
71#ifdef IMAGE_BL2
72static const mmap_region_t plat_rpi3_mmap[] = {
Andre Przywara0467ce92019-07-15 08:58:23 +010073#ifdef MAP_SHARED_RAM
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000074 MAP_SHARED_RAM,
Andre Przywara0467ce92019-07-15 08:58:23 +010075#endif
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000076 MAP_DEVICE0,
77 MAP_FIP,
78 MAP_NS_DRAM0,
79#ifdef BL32_BASE
80 MAP_BL32_MEM,
81#endif
82 {0}
83};
84#endif
85
86#ifdef IMAGE_BL31
87static const mmap_region_t plat_rpi3_mmap[] = {
Andre Przywara0467ce92019-07-15 08:58:23 +010088#ifdef MAP_SHARED_RAM
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000089 MAP_SHARED_RAM,
Andre Przywara0467ce92019-07-15 08:58:23 +010090#endif
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000091 MAP_DEVICE0,
Antonio Nino Diazf96582a2018-10-19 00:57:16 +010092#ifdef RPI3_PRELOADED_DTB_BASE
93 MAP_NS_DTB,
94#endif
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000095#ifdef BL32_BASE
96 MAP_BL32_MEM,
97#endif
98 {0}
99};
100#endif
101
102/*******************************************************************************
Antonio Nino Diaz1f470022018-03-27 09:39:47 +0100103 * Function that sets up the console
104 ******************************************************************************/
105static console_16550_t rpi3_console;
106
Andre Przywarafaf86182019-08-04 10:46:21 +0100107void rpi3_console_init(unsigned int base_clk_rate)
Antonio Nino Diaz1f470022018-03-27 09:39:47 +0100108{
Pete Batardc9acd6c2018-11-13 13:14:26 +0000109 int console_scope = CONSOLE_FLAG_BOOT;
110#if RPI3_RUNTIME_UART != -1
111 console_scope |= CONSOLE_FLAG_RUNTIME;
112#endif
Antonio Nino Diaz1f470022018-03-27 09:39:47 +0100113 int rc = console_16550_register(PLAT_RPI3_UART_BASE,
Andre Przywarafaf86182019-08-04 10:46:21 +0100114 base_clk_rate,
Antonio Nino Diaz1f470022018-03-27 09:39:47 +0100115 PLAT_RPI3_UART_BAUDRATE,
116 &rpi3_console);
117 if (rc == 0) {
118 /*
119 * The crash console doesn't use the multi console API, it uses
120 * the core console functions directly. It is safe to call panic
121 * and let it print debug information.
122 */
123 panic();
124 }
125
Pete Batardc9acd6c2018-11-13 13:14:26 +0000126 console_set_scope(&rpi3_console.console, console_scope);
Antonio Nino Diaz1f470022018-03-27 09:39:47 +0100127}
128
129/*******************************************************************************
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000130 * Function that sets up the translation tables.
131 ******************************************************************************/
132void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
133 uintptr_t code_start, uintptr_t code_limit,
134 uintptr_t rodata_start, uintptr_t rodata_limit
135#if USE_COHERENT_MEM
136 , uintptr_t coh_start, uintptr_t coh_limit
137#endif
138 )
139{
140 /*
141 * Map the Trusted SRAM with appropriate memory attributes.
142 * Subsequent mappings will adjust the attributes for specific regions.
143 */
144 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
145 (void *) total_base, (void *) (total_base + total_size));
146 mmap_add_region(total_base, total_base,
147 total_size,
148 MT_MEMORY | MT_RW | MT_SECURE);
149
150 /* Re-map the code section */
151 VERBOSE("Code region: %p - %p\n",
152 (void *) code_start, (void *) code_limit);
153 mmap_add_region(code_start, code_start,
154 code_limit - code_start,
155 MT_CODE | MT_SECURE);
156
157 /* Re-map the read-only data section */
158 VERBOSE("Read-only data region: %p - %p\n",
159 (void *) rodata_start, (void *) rodata_limit);
160 mmap_add_region(rodata_start, rodata_start,
161 rodata_limit - rodata_start,
162 MT_RO_DATA | MT_SECURE);
163
164#if USE_COHERENT_MEM
165 /* Re-map the coherent memory region */
166 VERBOSE("Coherent region: %p - %p\n",
167 (void *) coh_start, (void *) coh_limit);
168 mmap_add_region(coh_start, coh_start,
169 coh_limit - coh_start,
170 MT_DEVICE | MT_RW | MT_SECURE);
171#endif
172
173 mmap_add(plat_rpi3_mmap);
174
175 init_xlat_tables();
176}
177
178/*******************************************************************************
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000179 * Gets SPSR for BL32 entry
180 ******************************************************************************/
181uint32_t rpi3_get_spsr_for_bl32_entry(void)
182{
183 /*
184 * The Secure Payload Dispatcher service is responsible for
185 * setting the SPSR prior to entry into the BL32 image.
186 */
187 return 0;
188}
189
190/*******************************************************************************
191 * Gets SPSR for BL33 entry
192 ******************************************************************************/
193uint32_t rpi3_get_spsr_for_bl33_entry(void)
194{
195#if RPI3_BL33_IN_AARCH32
196 INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n");
197 return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE,
198 DISABLE_ALL_EXCEPTIONS);
199#else
200 return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
201#endif
202}
203
204unsigned int plat_get_syscnt_freq2(void)
205{
206 return SYS_COUNTER_FREQ_IN_TICKS;
207}
208
209uint32_t plat_ic_get_pending_interrupt_type(void)
210{
Antonio Nino Diaz9abd78d2018-07-11 21:00:32 +0100211 ERROR("rpi3: Interrupt routed to EL3.\n");
Antonio Nino Diazae6779e2017-11-06 14:49:04 +0000212 return INTR_TYPE_INVAL;
213}
Ying-Chun Liu (PaulLiu)d9f76e62018-06-10 02:00:27 +0800214
Antonio Nino Diaz9abd78d2018-07-11 21:00:32 +0100215uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
Ying-Chun Liu (PaulLiu)d9f76e62018-06-10 02:00:27 +0800216{
Antonio Nino Diaz9abd78d2018-07-11 21:00:32 +0100217 assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) ||
218 (type == INTR_TYPE_NS));
219
220 assert(sec_state_is_valid(security_state));
221
222 /* Non-secure interrupts are signalled on the IRQ line always. */
223 if (type == INTR_TYPE_NS)
224 return __builtin_ctz(SCR_IRQ_BIT);
225
226 /* Secure interrupts are signalled on the FIQ line always. */
227 return __builtin_ctz(SCR_FIQ_BIT);
Ying-Chun Liu (PaulLiu)d9f76e62018-06-10 02:00:27 +0800228}