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Soby Mathew0d786072016-03-24 16:56:29 +00001/*
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekar0a176e32020-02-13 13:07:12 -08003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Soby Mathew0d786072016-03-24 16:56:29 +00004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew0d786072016-03-24 16:56:29 +00006 */
7
Soby Mathew0d786072016-03-24 16:56:29 +00008#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <arch.h>
11#include <lib/pmf/pmf.h>
12#include <lib/psci/psci.h>
Varun Wadekar0a176e32020-02-13 13:07:12 -080013#include <lib/utils_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <plat/common/platform.h>
Soby Mathew0d786072016-03-24 16:56:29 +000015
dp-arm66abfbe2017-01-31 13:01:04 +000016#if ENABLE_PSCI_STAT && ENABLE_PMF
17#pragma weak plat_psci_stat_accounting_start
18#pragma weak plat_psci_stat_accounting_stop
19#pragma weak plat_psci_stat_get_residency
20
Soby Mathew8336f682017-10-16 15:19:31 +010021/* Maximum time-stamp value read from architectural counters */
Julius Werner8e0ef0f2019-07-09 14:02:43 -070022#ifdef __aarch64__
Soby Mathew8336f682017-10-16 15:19:31 +010023#define MAX_TS UINT64_MAX
Julius Werner8e0ef0f2019-07-09 14:02:43 -070024#else
25#define MAX_TS UINT32_MAX
Soby Mathew8336f682017-10-16 15:19:31 +010026#endif
27
dp-arm66abfbe2017-01-31 13:01:04 +000028/* Following are used as ID's to capture time-stamp */
29#define PSCI_STAT_ID_ENTER_LOW_PWR 0
30#define PSCI_STAT_ID_EXIT_LOW_PWR 1
31#define PSCI_STAT_TOTAL_IDS 2
32
Madhukar Pappireddya091d042020-01-06 14:42:30 -060033PMF_DECLARE_CAPTURE_TIMESTAMP(psci_svc)
34PMF_DECLARE_GET_TIMESTAMP(psci_svc)
dp-arm66abfbe2017-01-31 13:01:04 +000035PMF_REGISTER_SERVICE(psci_svc, PMF_PSCI_STAT_SVC_ID, PSCI_STAT_TOTAL_IDS,
36 PMF_STORE_ENABLE)
37
38/*
39 * This function calculates the stats residency in microseconds,
40 * taking in account the wrap around condition.
41 */
42static u_register_t calc_stat_residency(unsigned long long pwrupts,
43 unsigned long long pwrdnts)
44{
45 /* The divisor to use to convert raw timestamp into microseconds. */
46 u_register_t residency_div;
47 u_register_t res;
48
49 /*
50 * Calculate divisor so that it can be directly used to
51 * convert time-stamp into microseconds.
52 */
53 residency_div = read_cntfrq_el0() / MHZ_TICKS_PER_SEC;
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010054 assert(residency_div > 0U);
dp-arm66abfbe2017-01-31 13:01:04 +000055
56 if (pwrupts < pwrdnts)
Soby Mathew8336f682017-10-16 15:19:31 +010057 res = MAX_TS - pwrdnts + pwrupts;
dp-arm66abfbe2017-01-31 13:01:04 +000058 else
59 res = pwrupts - pwrdnts;
60
61 return res / residency_div;
62}
63
64/*
65 * Capture timestamp before entering a low power state.
66 * No cache maintenance is required when capturing the timestamp.
67 * Cache maintenance may be needed when reading these timestamps.
68 */
69void plat_psci_stat_accounting_start(
70 __unused const psci_power_state_t *state_info)
71{
Antonio Nino Diazfec756f2018-07-18 16:24:16 +010072 assert(state_info != NULL);
dp-arm66abfbe2017-01-31 13:01:04 +000073 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR,
74 PMF_NO_CACHE_MAINT);
75}
76
77/*
78 * Capture timestamp after exiting a low power state.
79 * No cache maintenance is required when capturing the timestamp.
80 * Cache maintenance may be needed when reading these timestamps.
81 */
82void plat_psci_stat_accounting_stop(
83 __unused const psci_power_state_t *state_info)
84{
Antonio Nino Diazfec756f2018-07-18 16:24:16 +010085 assert(state_info != NULL);
dp-arm66abfbe2017-01-31 13:01:04 +000086 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR,
87 PMF_NO_CACHE_MAINT);
88}
89
90/*
91 * Calculate the residency for the given level and power state
92 * information.
93 */
94u_register_t plat_psci_stat_get_residency(unsigned int lvl,
95 const psci_power_state_t *state_info,
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060096 unsigned int last_cpu_idx)
dp-arm66abfbe2017-01-31 13:01:04 +000097{
98 plat_local_state_t state;
99 unsigned long long pwrup_ts = 0, pwrdn_ts = 0;
100 unsigned int pmf_flags;
101
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100102 assert((lvl >= PSCI_CPU_PWR_LVL) && (lvl <= PLAT_MAX_PWR_LVL));
103 assert(state_info != NULL);
104 assert(last_cpu_idx <= PLATFORM_CORE_COUNT);
dp-arm66abfbe2017-01-31 13:01:04 +0000105
106 if (lvl == PSCI_CPU_PWR_LVL)
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -0600107 assert(last_cpu_idx == plat_my_core_pos());
dp-arm66abfbe2017-01-31 13:01:04 +0000108
109 /*
110 * If power down is requested, then timestamp capture will
111 * be with caches OFF. Hence we have to do cache maintenance
112 * when reading the timestamp.
113 */
114 state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL];
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100115 if (is_local_state_off(state) != 0) {
dp-arm66abfbe2017-01-31 13:01:04 +0000116 pmf_flags = PMF_CACHE_MAINT;
117 } else {
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100118 assert(is_local_state_retn(state) == 1);
dp-arm66abfbe2017-01-31 13:01:04 +0000119 pmf_flags = PMF_NO_CACHE_MAINT;
120 }
121
122 PMF_GET_TIMESTAMP_BY_INDEX(psci_svc,
123 PSCI_STAT_ID_ENTER_LOW_PWR,
124 last_cpu_idx,
125 pmf_flags,
126 pwrdn_ts);
127
128 PMF_GET_TIMESTAMP_BY_INDEX(psci_svc,
129 PSCI_STAT_ID_EXIT_LOW_PWR,
130 plat_my_core_pos(),
131 pmf_flags,
132 pwrup_ts);
133
134 return calc_stat_residency(pwrup_ts, pwrdn_ts);
135}
136#endif /* ENABLE_PSCI_STAT && ENABLE_PMF */
137
Soby Mathew0d786072016-03-24 16:56:29 +0000138/*
139 * The PSCI generic code uses this API to let the platform participate in state
140 * coordination during a power management operation. It compares the platform
141 * specific local power states requested by each cpu for a given power domain
142 * and returns the coordinated target power state that the domain should
143 * enter. A platform assigns a number to a local power state. This default
144 * implementation assumes that the platform assigns these numbers in order of
145 * increasing depth of the power state i.e. for two power states X & Y, if X < Y
146 * then X represents a shallower power state than Y. As a result, the
147 * coordinated target local power state for a power domain will be the minimum
148 * of the requested local power states.
149 */
150plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
151 const plat_local_state_t *states,
152 unsigned int ncpu)
153{
154 plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100155 const plat_local_state_t *st = states;
156 unsigned int n = ncpu;
Soby Mathew0d786072016-03-24 16:56:29 +0000157
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100158 assert(ncpu > 0U);
Soby Mathew0d786072016-03-24 16:56:29 +0000159
160 do {
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100161 temp = *st;
162 st++;
Soby Mathew0d786072016-03-24 16:56:29 +0000163 if (temp < target)
164 target = temp;
Antonio Nino Diazfec756f2018-07-18 16:24:16 +0100165 n--;
166 } while (n > 0U);
Soby Mathew0d786072016-03-24 16:56:29 +0000167
168 return target;
169}