Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef T194_NVG_H |
| 8 | #define T194_NVG_H |
| 9 | |
| 10 | /** |
| 11 | * t194_nvg.h - Header for the NVIDIA Generic interface (NVG). |
| 12 | * Official documentation for this interface is included as part |
| 13 | * of the T194 TRM. |
| 14 | */ |
| 15 | |
| 16 | /** |
| 17 | * Current version - Major version increments may break backwards |
| 18 | * compatiblity and binary compatibility. Minor version increments |
| 19 | * occur when there is only new functionality. |
| 20 | */ |
| 21 | enum { |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 22 | TEGRA_NVG_VERSION_MAJOR = 6, |
| 23 | TEGRA_NVG_VERSION_MINOR = 4 |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 24 | }; |
| 25 | |
| 26 | typedef enum { |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 27 | TEGRA_NVG_CHANNEL_VERSION = 0, |
| 28 | TEGRA_NVG_CHANNEL_POWER_PERF = 1, |
| 29 | TEGRA_NVG_CHANNEL_POWER_MODES = 2, |
| 30 | TEGRA_NVG_CHANNEL_WAKE_TIME = 3, |
| 31 | TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, |
| 32 | TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, |
| 33 | TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, |
| 34 | TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, |
| 35 | TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, |
| 36 | TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, |
| 37 | TEGRA_NVG_CHANNEL_SHUTDOWN = 42, |
| 38 | TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, |
| 39 | TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, |
| 40 | TEGRA_NVG_CHANNEL_CC3_CTRL = 45, |
| 41 | TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, |
| 42 | TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, |
| 43 | TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, |
| 44 | TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, |
| 45 | TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, |
| 46 | TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, |
| 47 | TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, |
| 48 | TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, |
| 49 | TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, |
| 50 | TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60, |
| 51 | TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61, |
| 52 | TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62, |
| 53 | TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63, |
| 54 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64, |
| 55 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65, |
| 56 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66, |
| 57 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67, |
| 58 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68, |
| 59 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69, |
| 60 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70, |
| 61 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71, |
| 62 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72, |
| 63 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73, |
| 64 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74, |
| 65 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75, |
| 66 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76, |
| 67 | TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77, |
| 68 | TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78, |
| 69 | TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79, |
| 70 | |
| 71 | TEGRA_NVG_CHANNEL_LAST_INDEX |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 72 | } tegra_nvg_channel_id_t; |
| 73 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 74 | typedef enum { |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 75 | NVG_STAT_QUERY_SC7_ENTRIES = 1, |
| 76 | NVG_STAT_QUERY_CC6_ENTRIES = 6, |
| 77 | NVG_STAT_QUERY_CG7_ENTRIES = 7, |
| 78 | NVG_STAT_QUERY_C6_ENTRIES = 10, |
| 79 | NVG_STAT_QUERY_C7_ENTRIES = 14, |
| 80 | NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, |
| 81 | NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41, |
| 82 | NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46, |
| 83 | NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, |
| 84 | NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56, |
| 85 | NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM = 60, |
| 86 | NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM = 61, |
| 87 | NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM = 62, |
| 88 | NVG_STAT_QUERY_C6_ENTRY_TIME_SUM = 63, |
| 89 | NVG_STAT_QUERY_C7_ENTRY_TIME_SUM = 64, |
| 90 | NVG_STAT_QUERY_SC7_EXIT_TIME_SUM = 70, |
| 91 | NVG_STAT_QUERY_CC6_EXIT_TIME_SUM = 71, |
| 92 | NVG_STAT_QUERY_CG7_EXIT_TIME_SUM = 72, |
| 93 | NVG_STAT_QUERY_C6_EXIT_TIME_SUM = 73, |
| 94 | NVG_STAT_QUERY_C7_EXIT_TIME_SUM = 74, |
| 95 | NVG_STAT_QUERY_SC7_ENTRY_LAST = 80, |
| 96 | NVG_STAT_QUERY_CC6_ENTRY_LAST = 81, |
| 97 | NVG_STAT_QUERY_CG7_ENTRY_LAST = 82, |
| 98 | NVG_STAT_QUERY_C6_ENTRY_LAST = 83, |
| 99 | NVG_STAT_QUERY_C7_ENTRY_LAST = 84, |
| 100 | NVG_STAT_QUERY_SC7_EXIT_LAST = 90, |
| 101 | NVG_STAT_QUERY_CC6_EXIT_LAST = 91, |
| 102 | NVG_STAT_QUERY_CG7_EXIT_LAST = 92, |
| 103 | NVG_STAT_QUERY_C6_EXIT_LAST = 93, |
| 104 | NVG_STAT_QUERY_C7_EXIT_LAST = 94 |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 105 | } tegra_nvg_stat_query_t; |
| 106 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 107 | typedef enum { |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 108 | TEGRA_NVG_CORE_C0 = 0, |
| 109 | TEGRA_NVG_CORE_C1 = 1, |
| 110 | TEGRA_NVG_CORE_C6 = 6, |
| 111 | TEGRA_NVG_CORE_C7 = 7, |
| 112 | TEGRA_NVG_CORE_WARMRSTREQ = 8 |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 113 | } tegra_nvg_core_sleep_state_t; |
| 114 | |
| 115 | typedef enum { |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 116 | TEGRA_NVG_CLUSTER_CC0 = 0, |
| 117 | TEGRA_NVG_CLUSTER_CC6 = 6 |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 118 | } tegra_nvg_cluster_sleep_state_t; |
| 119 | |
| 120 | typedef enum { |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 121 | TEGRA_NVG_CG_CG0 = 0, |
| 122 | TEGRA_NVG_CG_CG7 = 7 |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 123 | } tegra_nvg_cluster_group_sleep_state_t; |
| 124 | |
| 125 | typedef enum { |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 126 | TEGRA_NVG_SYSTEM_SC0 = 0, |
| 127 | TEGRA_NVG_SYSTEM_SC7 = 7, |
| 128 | TEGRA_NVG_SYSTEM_SC8 = 8 |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 129 | } tegra_nvg_system_sleep_state_t; |
| 130 | |
| 131 | // --------------------------------------------------------------------------- |
| 132 | // NVG Data subformats |
| 133 | // --------------------------------------------------------------------------- |
| 134 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 135 | typedef union { |
| 136 | uint64_t flat; |
| 137 | struct nvg_version_channel_t { |
| 138 | uint32_t minor_version : 32; |
| 139 | uint32_t major_version : 32; |
| 140 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 141 | } nvg_version_data_t; |
| 142 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 143 | typedef union { |
| 144 | uint64_t flat; |
| 145 | struct nvg_power_perf_channel_t { |
| 146 | uint32_t perf_per_watt : 1; |
| 147 | uint32_t reserved_31_1 : 31; |
| 148 | uint32_t reserved_63_32 : 32; |
| 149 | } bits; |
| 150 | } nvg_power_perf_channel_t; |
| 151 | |
| 152 | typedef union { |
| 153 | uint64_t flat; |
| 154 | struct nvg_power_modes_channel_t { |
| 155 | uint32_t low_battery : 1; |
| 156 | uint32_t reserved_1_1 : 1; |
| 157 | uint32_t battery_save : 1; |
| 158 | uint32_t reserved_31_3 : 29; |
| 159 | uint32_t reserved_63_32 : 32; |
| 160 | } bits; |
| 161 | } nvg_power_modes_channel_t; |
| 162 | |
| 163 | typedef union nvg_channel_1_data_u { |
| 164 | uint64_t flat; |
| 165 | struct nvg_channel_1_data_s { |
| 166 | uint32_t perf_per_watt_mode : 1; |
| 167 | uint32_t reserved_31_1 : 31; |
| 168 | uint32_t reserved_63_32 : 32; |
| 169 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 170 | } nvg_channel_1_data_t; |
| 171 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 172 | typedef union { |
| 173 | uint64_t flat; |
| 174 | struct nvg_ccplex_cache_control_channel_t { |
| 175 | uint32_t gpu_ways : 5; |
| 176 | uint32_t reserved_7_5 : 3; |
| 177 | uint32_t gpu_only_ways : 5; |
| 178 | uint32_t reserved_31_13 : 19; |
| 179 | uint32_t reserved_63_32 : 32; |
| 180 | } bits; |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 181 | } nvg_ccplex_cache_control_channel_t; |
| 182 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 183 | typedef union nvg_channel_2_data_u { |
| 184 | uint64_t flat; |
| 185 | struct nvg_channel_2_data_s { |
| 186 | uint32_t reserved_1_0 : 2; |
| 187 | uint32_t battery_saver_mode : 1; |
| 188 | uint32_t reserved_31_3 : 29; |
| 189 | uint32_t reserved_63_32 : 32; |
| 190 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 191 | } nvg_channel_2_data_t; |
| 192 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 193 | typedef union { |
| 194 | uint64_t flat; |
| 195 | struct nvg_wake_time_channel_t { |
| 196 | uint32_t wake_time : 32; |
| 197 | uint32_t reserved_63_32 : 32; |
| 198 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 199 | } nvg_wake_time_channel_t; |
| 200 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 201 | typedef union { |
| 202 | uint64_t flat; |
| 203 | struct nvg_cstate_info_channel_t { |
| 204 | uint32_t cluster_state : 3; |
| 205 | uint32_t reserved_6_3 : 4; |
| 206 | uint32_t update_cluster : 1; |
| 207 | uint32_t cg_cstate : 3; |
| 208 | uint32_t reserved_14_11 : 4; |
| 209 | uint32_t update_cg : 1; |
| 210 | uint32_t system_cstate : 4; |
| 211 | uint32_t reserved_22_20 : 3; |
| 212 | uint32_t update_system : 1; |
| 213 | uint32_t reserved_30_24 : 7; |
| 214 | uint32_t update_wake_mask : 1; |
| 215 | uint32_t wake_mask : 32; |
| 216 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 217 | } nvg_cstate_info_channel_t; |
| 218 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 219 | typedef union { |
| 220 | uint64_t flat; |
| 221 | struct nvg_lower_bound_channel_t { |
| 222 | uint32_t crossover_value : 32; |
| 223 | uint32_t reserved_63_32 : 32; |
| 224 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 225 | } nvg_lower_bound_channel_t; |
| 226 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 227 | typedef union { |
| 228 | uint64_t flat; |
| 229 | struct nvg_cstate_stat_query_channel_t { |
| 230 | uint32_t unit_id : 4; |
| 231 | uint32_t reserved_15_4 : 12; |
| 232 | uint32_t stat_id : 16; |
| 233 | uint32_t reserved_63_32 : 32; |
| 234 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 235 | } nvg_cstate_stat_query_channel_t; |
| 236 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 237 | typedef union { |
| 238 | uint64_t flat; |
| 239 | struct nvg_is_sc7_allowed_channel_t { |
| 240 | uint32_t is_sc7_allowed : 1; |
| 241 | uint32_t reserved_31_1 : 31; |
| 242 | uint32_t reserved_63_32 : 32; |
| 243 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 244 | } nvg_is_sc7_allowed_channel_t; |
| 245 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 246 | typedef union { |
| 247 | uint64_t flat; |
| 248 | struct nvg_core_online_channel_t { |
| 249 | uint32_t core_id : 4; |
| 250 | uint32_t reserved_31_4 : 28; |
| 251 | uint32_t reserved_63_32 : 32; |
| 252 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 253 | } nvg_core_online_channel_t; |
| 254 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 255 | typedef union { |
| 256 | uint64_t flat; |
| 257 | struct nvg_cc3_control_channel_t { |
| 258 | uint32_t freq_req : 8; |
| 259 | uint32_t reserved_30_8 : 23; |
| 260 | uint32_t enable : 1; |
| 261 | uint32_t reserved_63_32 : 32; |
| 262 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 263 | } nvg_cc3_control_channel_t; |
| 264 | |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 265 | typedef enum { |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 266 | TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0, |
| 267 | TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1, |
| 268 | TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2, |
| 269 | TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3, |
| 270 | TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4, |
| 271 | TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5, |
| 272 | TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6, |
| 273 | TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7, |
| 274 | TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8, |
| 275 | TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9, |
| 276 | TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, |
| 277 | TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, |
| 278 | TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, |
| 279 | TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, |
| 280 | TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, |
| 281 | TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, |
| 282 | TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, |
| 283 | TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, |
| 284 | TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, |
| 285 | TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, |
| 286 | TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, |
| 287 | TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, |
| 288 | TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, |
| 289 | TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, |
| 290 | TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, |
| 291 | TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, |
| 292 | TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, |
| 293 | TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, |
| 294 | TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, |
| 295 | TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, |
| 296 | TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, |
| 297 | TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, |
| 298 | TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, |
| 299 | TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, |
| 300 | TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, |
| 301 | TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, |
| 302 | TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 303 | } tegra_nvg_channel_update_gsc_gsc_enum_t; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 304 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 305 | typedef union { |
| 306 | uint64_t flat; |
| 307 | struct nvg_update_ccplex_gsc_channel_t { |
| 308 | uint32_t gsc_enum : 16; |
| 309 | uint32_t reserved_31_16 : 16; |
| 310 | uint32_t reserved_63_32 : 32; |
| 311 | } bits; |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 312 | } nvg_update_ccplex_gsc_channel_t; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 313 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 314 | typedef union { |
| 315 | uint64_t flat; |
| 316 | struct nvg_security_config_channel_t { |
| 317 | uint32_t strict_checking_enabled : 1; |
| 318 | uint32_t strict_checking_locked : 1; |
| 319 | uint32_t reserved_31_2 : 30; |
| 320 | uint32_t reserved_63_32 : 32; |
| 321 | } bits; |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 322 | } nvg_security_config_t; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 323 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 324 | typedef union { |
| 325 | uint64_t flat; |
| 326 | struct nvg_shutdown_channel_t { |
| 327 | uint32_t reboot : 1; |
| 328 | uint32_t reserved_31_1 : 31; |
| 329 | uint32_t reserved_63_32 : 32; |
| 330 | } bits; |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 331 | } nvg_shutdown_t; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 332 | |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 333 | #endif |