| Ghennadi Procopciuc | 9dee8e4 | 2024-06-12 09:25:17 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: BSD-3-Clause |
| 2 | /* |
| 3 | * Copyright 2020-2021, 2023-2024 NXP |
| 4 | */ |
| 5 | #ifndef S32CC_CLK_REGS_H |
| 6 | #define S32CC_CLK_REGS_H |
| 7 | |
| 8 | #include <lib/utils_def.h> |
| 9 | |
| 10 | #define FXOSC_BASE_ADDR (0x40050000UL) |
| 11 | |
| 12 | /* FXOSC */ |
| 13 | #define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL) |
| 14 | #define FXOSC_CTRL_OSC_BYP BIT_32(31U) |
| 15 | #define FXOSC_CTRL_COMP_EN BIT_32(24U) |
| 16 | #define FXOSC_CTRL_EOCV_OFFSET 16U |
| 17 | #define FXOSC_CTRL_EOCV_MASK GENMASK_32(23U, FXOSC_CTRL_EOCV_OFFSET) |
| 18 | #define FXOSC_CTRL_EOCV(VAL) (FXOSC_CTRL_EOCV_MASK & \ |
| 19 | ((uint32_t)(VAL) << FXOSC_CTRL_EOCV_OFFSET)) |
| 20 | #define FXOSC_CTRL_GM_SEL_OFFSET 4U |
| 21 | #define FXOSC_CTRL_GM_SEL_MASK GENMASK_32(7U, FXOSC_CTRL_GM_SEL_OFFSET) |
| 22 | #define FXOSC_CTRL_GM_SEL(VAL) (FXOSC_CTRL_GM_SEL_MASK & \ |
| 23 | ((uint32_t)(VAL) << FXOSC_CTRL_GM_SEL_OFFSET)) |
| 24 | #define FXOSC_CTRL_OSCON BIT_32(0U) |
| 25 | |
| 26 | #define FXOSC_STAT(FXOSC) ((FXOSC) + 0x4UL) |
| 27 | #define FXOSC_STAT_OSC_STAT BIT_32(31U) |
| 28 | |
| 29 | #endif /* S32CC_CLK_REGS_H */ |