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Haojian Zhuang5f281b32017-05-24 08:45:05 +08001/*
Haojian Zhuang92c3b822018-01-28 23:00:15 +08002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang5f281b32017-05-24 08:45:05 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <arm_gic.h>
9#include <assert.h>
10#include <bl_common.h>
11#include <debug.h>
12#include <mmio.h>
13#include <platform.h>
14#include <platform_def.h>
15#include <xlat_tables.h>
16
17#include "../hikey_def.h"
18
19#define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \
Haojian Zhuang92c3b822018-01-28 23:00:15 +080020 DDR_SIZE - DDR_SEC_SIZE, \
Haojian Zhuang5f281b32017-05-24 08:45:05 +080021 MT_DEVICE | MT_RW | MT_NS)
22
23#define MAP_DEVICE MAP_REGION_FLAT(DEVICE_BASE, \
24 DEVICE_SIZE, \
25 MT_DEVICE | MT_RW | MT_SECURE)
26
Victor Chongb9a8db22017-05-28 00:14:25 +090027#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
28 TSP_SEC_MEM_SIZE, \
29 MT_MEMORY | MT_RW | MT_SECURE)
30
Haojian Zhuang5f281b32017-05-24 08:45:05 +080031#define MAP_ROM_PARAM MAP_REGION_FLAT(XG2RAM0_BASE, \
32 BL1_XG2RAM0_OFFSET, \
33 MT_DEVICE | MT_RO | MT_SECURE)
34
35#define MAP_SRAM MAP_REGION_FLAT(SRAM_BASE, \
36 SRAM_SIZE, \
37 MT_DEVICE | MT_RW | MT_SECURE)
38
39/*
40 * BL1 needs to access the areas of MMC_SRAM.
41 * BL1 loads BL2 from eMMC into SRAM before DDR initialized.
42 */
43#define MAP_MMC_SRAM MAP_REGION_FLAT(HIKEY_BL1_MMC_DESC_BASE, \
44 HIKEY_BL1_MMC_DESC_SIZE + \
45 HIKEY_BL1_MMC_DATA_SIZE, \
46 MT_DEVICE | MT_RW | MT_SECURE)
47
48/*
49 * Table of regions for different BL stages to map using the MMU.
50 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
51 * hikey_init_mmu_elx() will give the available subset of that,
52 */
Roberto Vargas82477962017-10-23 08:22:17 +010053#ifdef IMAGE_BL1
Haojian Zhuang5f281b32017-05-24 08:45:05 +080054static const mmap_region_t hikey_mmap[] = {
55 MAP_DEVICE,
56 MAP_ROM_PARAM,
57 MAP_MMC_SRAM,
58 {0}
59};
60#endif
61
Roberto Vargas82477962017-10-23 08:22:17 +010062#ifdef IMAGE_BL2
Haojian Zhuang5f281b32017-05-24 08:45:05 +080063static const mmap_region_t hikey_mmap[] = {
64 MAP_DDR,
65 MAP_DEVICE,
Victor Chongb9a8db22017-05-28 00:14:25 +090066 MAP_TSP_MEM,
Haojian Zhuangb755da32018-01-25 16:10:14 +080067 MAP_SRAM,
Haojian Zhuang5f281b32017-05-24 08:45:05 +080068 {0}
69};
70#endif
71
Roberto Vargas82477962017-10-23 08:22:17 +010072#ifdef IMAGE_BL31
Haojian Zhuang5f281b32017-05-24 08:45:05 +080073static const mmap_region_t hikey_mmap[] = {
74 MAP_DEVICE,
75 MAP_SRAM,
Victor Chongb9a8db22017-05-28 00:14:25 +090076 MAP_TSP_MEM,
77 {0}
78};
79#endif
80
Roberto Vargas82477962017-10-23 08:22:17 +010081#ifdef IMAGE_BL32
Victor Chongb9a8db22017-05-28 00:14:25 +090082static const mmap_region_t hikey_mmap[] = {
83 MAP_DEVICE,
84 MAP_DDR,
Haojian Zhuang5f281b32017-05-24 08:45:05 +080085 {0}
86};
87#endif
88
89/*
90 * Macro generating the code for the function setting up the pagetables as per
91 * the platform memory map & initialize the mmu, for the given exception level
92 */
93#define HIKEY_CONFIGURE_MMU_EL(_el) \
94 void hikey_init_mmu_el##_el(unsigned long total_base, \
95 unsigned long total_size, \
96 unsigned long ro_start, \
97 unsigned long ro_limit, \
98 unsigned long coh_start, \
99 unsigned long coh_limit) \
100 { \
101 mmap_add_region(total_base, total_base, \
102 total_size, \
103 MT_MEMORY | MT_RW | MT_SECURE); \
104 mmap_add_region(ro_start, ro_start, \
105 ro_limit - ro_start, \
106 MT_MEMORY | MT_RO | MT_SECURE); \
107 mmap_add_region(coh_start, coh_start, \
108 coh_limit - coh_start, \
109 MT_DEVICE | MT_RW | MT_SECURE); \
110 mmap_add(hikey_mmap); \
111 init_xlat_tables(); \
112 \
113 enable_mmu_el##_el(0); \
114 }
115
116/* Define EL1 and EL3 variants of the function initialising the MMU */
117HIKEY_CONFIGURE_MMU_EL(1)
118HIKEY_CONFIGURE_MMU_EL(3)
119
120unsigned long plat_get_ns_image_entrypoint(void)
121{
122 return HIKEY_NS_IMAGE_OFFSET;
123}
124
125unsigned int plat_get_syscnt_freq2(void)
126{
127 return 1200000;
128}