blob: d20a683b3b569652bd32125f1bd3d7a3a5fa07d8 [file] [log] [blame]
Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
32#include <assert.h>
33#include <console.h>
34#include <errno.h>
35#include <debug.h>
36#include <psci.h>
37#include <delay_timer.h>
38#include <platform_def.h>
39#include <plat_private.h>
40
41/* Macros to read the rk power domain state */
42#define RK_CORE_PWR_STATE(state) \
43 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
44#define RK_CLUSTER_PWR_STATE(state) \
45 ((state)->pwr_domain_state[MPIDR_AFFLVL1])
46#define RK_SYSTEM_PWR_STATE(state) \
47 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
48
49static uintptr_t rockchip_sec_entrypoint;
50
51static struct rockchip_pm_ops_cb *rockchip_ops;
52
53static void plat_rockchip_sys_pwr_domain_resume(void)
54{
Tony Xief6118cc2016-01-15 17:17:32 +080055 if (rockchip_ops && rockchip_ops->sys_pwr_dm_resume)
56 rockchip_ops->sys_pwr_dm_resume();
57}
58
59static void plat_rockchip_cores_pwr_domain_resume(void)
60{
61 if (rockchip_ops && rockchip_ops->cores_pwr_dm_resume)
62 rockchip_ops->cores_pwr_dm_resume();
63
Tony Xief6118cc2016-01-15 17:17:32 +080064 /* Program the gic per-cpu distributor or re-distributor interface */
65 plat_rockchip_gic_cpuif_enable();
66}
67
68/*******************************************************************************
69 * Rockchip standard platform handler called to check the validity of the power
70 * state parameter.
71 ******************************************************************************/
72int rockchip_validate_power_state(unsigned int power_state,
73 psci_power_state_t *req_state)
74{
75 int pstate = psci_get_pstate_type(power_state);
76 int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
77 int i;
78
79 assert(req_state);
80
81 if (pwr_lvl > PLAT_MAX_PWR_LVL)
82 return PSCI_E_INVALID_PARAMS;
83
84 /* Sanity check the requested state */
85 if (pstate == PSTATE_TYPE_STANDBY) {
86 /*
87 * It's probably to enter standby only on power level 0
88 * ignore any other power level.
89 */
90 if (pwr_lvl != MPIDR_AFFLVL0)
91 return PSCI_E_INVALID_PARAMS;
92
93 req_state->pwr_domain_state[MPIDR_AFFLVL0] =
94 PLAT_MAX_RET_STATE;
95 } else {
96 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++)
97 req_state->pwr_domain_state[i] =
98 PLAT_MAX_OFF_STATE;
99 }
100
101 /* We expect the 'state id' to be zero */
102 if (psci_get_pstate_id(power_state))
103 return PSCI_E_INVALID_PARAMS;
104
105 return PSCI_E_SUCCESS;
106}
107
108void rockchip_get_sys_suspend_power_state(psci_power_state_t *req_state)
109{
110 int i;
111
112 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
113 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
114}
115
116/*******************************************************************************
117 * RockChip handler called when a CPU is about to enter standby.
118 ******************************************************************************/
119void rockchip_cpu_standby(plat_local_state_t cpu_state)
120{
121 unsigned int scr;
122
123 assert(cpu_state == PLAT_MAX_RET_STATE);
124
125 scr = read_scr_el3();
126 /* Enable PhysicalIRQ bit for NS world to wake the CPU */
127 write_scr_el3(scr | SCR_IRQ_BIT);
128 isb();
129 dsb();
130 wfi();
131
132 /*
133 * Restore SCR to the original value, synchronisation of scr_el3 is
134 * done by eret while el3_exit to save some execution cycles.
135 */
136 write_scr_el3(scr);
137}
138
139/*******************************************************************************
140 * RockChip handler called when a power domain is about to be turned on. The
141 * mpidr determines the CPU to be turned on.
142 ******************************************************************************/
143int rockchip_pwr_domain_on(u_register_t mpidr)
144{
145 if (rockchip_ops && rockchip_ops->cores_pwr_dm_on)
146 rockchip_ops->cores_pwr_dm_on(mpidr, rockchip_sec_entrypoint);
147
148 return PSCI_E_SUCCESS;
149}
150
151/*******************************************************************************
152 * RockChip handler called when a power domain is about to be turned off. The
153 * target_state encodes the power state that each level should transition to.
154 ******************************************************************************/
155void rockchip_pwr_domain_off(const psci_power_state_t *target_state)
156{
157 assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE);
158
159 plat_rockchip_gic_cpuif_disable();
160
161 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
162 plat_cci_disable();
163 if (rockchip_ops && rockchip_ops->cores_pwr_dm_off)
164 rockchip_ops->cores_pwr_dm_off();
165}
166
167/*******************************************************************************
168 * RockChip handler called when a power domain is about to be suspended. The
169 * target_state encodes the power state that each level should transition to.
170 ******************************************************************************/
171void rockchip_pwr_domain_suspend(const psci_power_state_t *target_state)
172{
173 if (RK_CORE_PWR_STATE(target_state) == PLAT_MAX_RET_STATE)
174 return;
175
176 assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE);
177
178 if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
179 if (rockchip_ops && rockchip_ops->sys_pwr_dm_suspend)
180 rockchip_ops->sys_pwr_dm_suspend();
181 } else {
182 if (rockchip_ops && rockchip_ops->cores_pwr_dm_suspend)
183 rockchip_ops->cores_pwr_dm_suspend();
184 }
185
186 /* Prevent interrupts from spuriously waking up this cpu */
187 plat_rockchip_gic_cpuif_disable();
188
189 /* Perform the common cluster specific operations */
190 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
191 plat_cci_disable();
192}
193
194/*******************************************************************************
195 * RockChip handler called when a power domain has just been powered on after
196 * being turned off earlier. The target_state encodes the low power state that
197 * each level has woken up from.
198 ******************************************************************************/
199void rockchip_pwr_domain_on_finish(const psci_power_state_t *target_state)
200{
201 assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE);
202
203 if (rockchip_ops && rockchip_ops->cores_pwr_dm_on_finish)
204 rockchip_ops->cores_pwr_dm_on_finish();
205
206 /* Perform the common cluster specific operations */
207 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
208 /* Enable coherency if this cluster was off */
209 plat_cci_enable();
210 }
211
212 /* Enable the gic cpu interface */
213 plat_rockchip_gic_pcpu_init();
214
215 /* Program the gic per-cpu distributor or re-distributor interface */
216 plat_rockchip_gic_cpuif_enable();
217}
218
219/*******************************************************************************
220 * RockChip handler called when a power domain has just been powered on after
221 * having been suspended earlier. The target_state encodes the low power state
222 * that each level has woken up from.
223 * TODO: At the moment we reuse the on finisher and reinitialize the secure
224 * context. Need to implement a separate suspend finisher.
225 ******************************************************************************/
226void rockchip_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
227{
228 /* Nothing to be done on waking up from retention from CPU level */
229 if (RK_CORE_PWR_STATE(target_state) == PLAT_MAX_RET_STATE)
230 return;
231
232 /* Perform system domain restore if woken up from system suspend */
233 if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
234 plat_rockchip_sys_pwr_domain_resume();
235 else
236 plat_rockchip_cores_pwr_domain_resume();
237
238 /* Perform the common cluster specific operations */
239 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
240 /* Enable coherency if this cluster was off */
241 plat_cci_enable();
242 }
243}
244
245/*******************************************************************************
246 * RockChip handlers to reboot the system
247 ******************************************************************************/
248static void __dead2 rockchip_system_reset(void)
249{
250 assert(rockchip_ops && rockchip_ops->sys_gbl_soft_reset);
251
252 rockchip_ops->sys_gbl_soft_reset();
253}
254
255/*******************************************************************************
Caesar Wangd1b9d2d2016-05-25 19:05:19 +0800256 * RockChip handlers to power off the system
257 ******************************************************************************/
258static void __dead2 rockchip_system_poweroff(void)
259{
260 assert(rockchip_ops && rockchip_ops->system_off);
261
262 rockchip_ops->system_off();
263}
264
265/*******************************************************************************
Tony Xief6118cc2016-01-15 17:17:32 +0800266 * Export the platform handlers via plat_rockchip_psci_pm_ops. The rockchip
267 * standard
268 * platform layer will take care of registering the handlers with PSCI.
269 ******************************************************************************/
270const plat_psci_ops_t plat_rockchip_psci_pm_ops = {
271 .cpu_standby = rockchip_cpu_standby,
272 .pwr_domain_on = rockchip_pwr_domain_on,
273 .pwr_domain_off = rockchip_pwr_domain_off,
274 .pwr_domain_suspend = rockchip_pwr_domain_suspend,
275 .pwr_domain_on_finish = rockchip_pwr_domain_on_finish,
276 .pwr_domain_suspend_finish = rockchip_pwr_domain_suspend_finish,
277 .system_reset = rockchip_system_reset,
Caesar Wangd1b9d2d2016-05-25 19:05:19 +0800278 .system_off = rockchip_system_poweroff,
Tony Xief6118cc2016-01-15 17:17:32 +0800279 .validate_power_state = rockchip_validate_power_state,
280 .get_sys_suspend_power_state = rockchip_get_sys_suspend_power_state
281};
282
283int plat_setup_psci_ops(uintptr_t sec_entrypoint,
284 const plat_psci_ops_t **psci_ops)
285{
286 *psci_ops = &plat_rockchip_psci_pm_ops;
287 rockchip_sec_entrypoint = sec_entrypoint;
288 return 0;
289}
290
291void plat_setup_rockchip_pm_ops(struct rockchip_pm_ops_cb *ops)
292{
293 rockchip_ops = ops;
294}