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Douglas Raillardd7c21b72017-06-28 15:23:03 +01001ARM Trusted Firmware User Guide
2===============================
3
4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
10This document describes how to build ARM Trusted Firmware (TF) and run it with a
11tested set of other software components using defined configurations on the Juno
12ARM development platform and ARM Fixed Virtual Platform (FVP) models. It is
13possible to use other software components, configurations and platforms but that
14is outside the scope of this document.
15
16This document assumes that the reader has previous experience running a fully
17bootable Linux software stack on Juno or FVP using the prebuilt binaries and
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010018filesystems provided by `Linaro`_. Further information may be found in the
19`Linaro instructions`_. It also assumes that the user understands the role of
20the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
22- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
23- Normal world bootloader (e.g. UEFI or U-Boot)
24- Device tree
25- Linux kernel image
26- Root filesystem
27
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010028This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029the different command line options available to launch the model.
30
31This document should be used in conjunction with the `Firmware Design`_.
32
33Host machine requirements
34-------------------------
35
36The minimum recommended machine specification for building the software and
37running the FVP models is a dual-core processor running at 2GHz with 12GB of
38RAM. For best performance, use a machine with a quad-core processor running at
392.6GHz with 16GB of RAM.
40
41The software has been tested on Ubuntu 14.04 LTS (64-bit). Packages used for
42building the software were installed from that distribution unless otherwise
43specified.
44
45The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010046Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047
48Tools
49-----
50
51Install the required packages to build Trusted Firmware with the following
52command:
53
54::
55
56 sudo apt-get install build-essential gcc make git libssl-dev
57
David Cunadob2de0992017-06-29 12:01:33 +010058ARM TF has been tested with `Linaro Release 17.04`_.
59
Douglas Raillardd7c21b72017-06-28 15:23:03 +010060Download and install the AArch32 or AArch64 little-endian GCC cross compiler.
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010061The `Linaro Release Notes`_ documents which version of the compiler to use for a
62given Linaro Release. Also, these `Linaro instructions`_ provide further
63guidance and a script, which can be used to download Linaro deliverables
64automatically.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010065
66Optionally, Trusted Firmware can be built using clang or ARM Compiler 6.
67See instructions below on how to switch the default compiler.
68
69In addition, the following optional packages and tools may be needed:
70
71- ``device-tree-compiler`` package if you need to rebuild the Flattened Device
72 Tree (FDT) source files (``.dts`` files) provided with this software.
73
74- For debugging, ARM `Development Studio 5 (DS-5)`_.
75
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010076- To create and modify the diagram files included in the documentation, `Dia`_.
77 This tool can be found in most Linux distributions. Inkscape is needed to
78 generate the actual *.png files.
79
Douglas Raillardd7c21b72017-06-28 15:23:03 +010080Getting the Trusted Firmware source code
81----------------------------------------
82
83Download the Trusted Firmware source code from Github:
84
85::
86
87 git clone https://github.com/ARM-software/arm-trusted-firmware.git
88
89Building the Trusted Firmware
90-----------------------------
91
92- Before building Trusted Firmware, the environment variable ``CROSS_COMPILE``
93 must point to the Linaro cross compiler.
94
95 For AArch64:
96
97 ::
98
99 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
100
101 For AArch32:
102
103 ::
104
105 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
106
107 It is possible to build Trusted Firmware using clang or ARM Compiler 6.
108 To do so ``CC`` needs to point to the clang or armclang binary. Only the
109 compiler is switched; the assembler and linker need to be provided by
110 the GNU toolchain, thus ``CROSS_COMPILE`` should be set as described above.
111
112 ARM Compiler 6 will be selected when the base name of the path assigned
113 to ``CC`` matches the string 'armclang'.
114
115 For AArch64 using ARM Compiler 6:
116
117 ::
118
119 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
120 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
121
122 Clang will be selected when the base name of the path assigned to ``CC``
123 contains the string 'clang'. This is to allow both clang and clang-X.Y
124 to work.
125
126 For AArch64 using clang:
127
128 ::
129
130 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
131 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
132
133- Change to the root directory of the Trusted Firmware source tree and build.
134
135 For AArch64:
136
137 ::
138
139 make PLAT=<platform> all
140
141 For AArch32:
142
143 ::
144
145 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
146
147 Notes:
148
149 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
150 `Summary of build options`_ for more information on available build
151 options.
152
153 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
154
155 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
156 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
157 provided by ARM Trusted Firmware to demonstrate how PSCI Library can
158 be integrated with an AArch32 EL3 Runtime Software. Some AArch32 EL3
159 Runtime Software may include other runtime services, for example
160 Trusted OS services. A guide to integrate PSCI library with AArch32
161 EL3 Runtime Software can be found `here`_.
162
163 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
164 image, is not compiled in by default. Refer to the
165 `Building the Test Secure Payload`_ section below.
166
167 - By default this produces a release version of the build. To produce a
168 debug version instead, refer to the "Debugging options" section below.
169
170 - The build process creates products in a ``build`` directory tree, building
171 the objects and binaries for each boot loader stage in separate
172 sub-directories. The following boot loader binary files are created
173 from the corresponding ELF files:
174
175 - ``build/<platform>/<build-type>/bl1.bin``
176 - ``build/<platform>/<build-type>/bl2.bin``
177 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
178 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
179
180 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
181 is either ``debug`` or ``release``. The actual number of images might differ
182 depending on the platform.
183
184- Build products for a specific build variant can be removed using:
185
186 ::
187
188 make DEBUG=<D> PLAT=<platform> clean
189
190 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
191
192 The build tree can be removed completely using:
193
194 ::
195
196 make realclean
197
198Summary of build options
199~~~~~~~~~~~~~~~~~~~~~~~~
200
201ARM Trusted Firmware build system supports the following build options. Unless
202mentioned otherwise, these options are expected to be specified at the build
203command line and are not to be modified in any component makefiles. Note that
204the build system doesn't track dependency for build options. Therefore, if any
205of the build options are changed from a previous build, a clean build must be
206performed.
207
208Common build options
209^^^^^^^^^^^^^^^^^^^^
210
211- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
212 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
213 directory containing the SP source, relative to the ``bl32/``; the directory
214 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
215
216- ``ARCH`` : Choose the target build architecture for ARM Trusted Firmware.
217 It can take either ``aarch64`` or ``aarch32`` as values. By default, it is
218 defined to ``aarch64``.
219
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100220- ``ARM_ARCH_MAJOR``: The major version of ARM Architecture to target when
221 compiling ARM Trusted Firmware. Its value must be numeric, and defaults to
222 8 . See also, *ARMv8 Architecture Extensions* in `Firmware Design`_.
223
224- ``ARM_ARCH_MINOR``: The minor version of ARM Architecture to target when
225 compiling ARM Trusted Firmware. Its value must be a numeric, and defaults
226 to 0. See also, *ARMv8 Architecture Extensions* in `Firmware Design`_.
227
228- ``ARM_GIC_ARCH``: Choice of ARM GIC architecture version used by the ARM
229 Legacy GIC driver for implementing the platform GIC API. This API is used
230 by the interrupt management framework. Default is 2 (that is, version 2.0).
231 This build option is deprecated.
232
233- ``ARM_PLAT_MT``: This flag determines whether the ARM platform layer has to
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000234 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
235 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
236 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
237 this flag is 0. Note that this option is not used on FVP platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100238
239- ``BL2``: This is an optional build option which specifies the path to BL2
240 image for the ``fip`` target. In this case, the BL2 in the ARM Trusted
241 Firmware will not be built.
242
243- ``BL2U``: This is an optional build option which specifies the path to
244 BL2U image. In this case, the BL2U in the ARM Trusted Firmware will not
245 be built.
246
247- ``BL31``: This is an optional build option which specifies the path to
248 BL31 image for the ``fip`` target. In this case, the BL31 in the ARM
249 Trusted Firmware will not be built.
250
251- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
252 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
253 this file name will be used to save the key.
254
255- ``BL32``: This is an optional build option which specifies the path to
256 BL32 image for the ``fip`` target. In this case, the BL32 in the ARM
257 Trusted Firmware will not be built.
258
Summer Qin80726782017-04-20 16:28:39 +0100259- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
260 Trusted OS Extra1 image for the ``fip`` target.
261
262- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
263 Trusted OS Extra2 image for the ``fip`` target.
264
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100265- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
266 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
267 this file name will be used to save the key.
268
269- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
270 ``fip`` target in case the BL2 from ARM Trusted Firmware is used.
271
272- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
273 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
274 this file name will be used to save the key.
275
276- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
277 compilation of each build. It must be set to a C string (including quotes
278 where applicable). Defaults to a string that contains the time and date of
279 the compilation.
280
281- ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF build
282 to be uniquely identified. Defaults to the current git commit id.
283
284- ``CFLAGS``: Extra user options appended on the compiler's command line in
285 addition to the options set by the build system.
286
287- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
288 release several CPUs out of reset. It can take either 0 (several CPUs may be
289 brought up) or 1 (only one CPU will ever be brought up during cold reset).
290 Default is 0. If the platform always brings up a single CPU, there is no
291 need to distinguish between primary and secondary CPUs and the boot path can
292 be optimised. The ``plat_is_my_cpu_primary()`` and
293 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
294 to be implemented in this case.
295
296- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
297 register state when an unexpected exception occurs during execution of
298 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
299 this is only enabled for a debug build of the firmware.
300
301- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
302 certificate generation tool to create new keys in case no valid keys are
303 present or specified. Allowed options are '0' or '1'. Default is '1'.
304
305- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
306 the AArch32 system registers to be included when saving and restoring the
307 CPU context. The option must be set to 0 for AArch64-only platforms (that
308 is on hardware that does not implement AArch32, or at least not at EL1 and
309 higher ELs). Default value is 1.
310
311- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
312 registers to be included when saving and restoring the CPU context. Default
313 is 0.
314
315- ``DEBUG``: Chooses between a debug and release build. It can take either 0
316 (release) or 1 (debug) as values. 0 is the default.
317
318- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
319 the normal boot flow. It must specify the entry point address of the EL3
320 payload. Please refer to the "Booting an EL3 payload" section for more
321 details.
322
323- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
324 are compiled out. For debug builds, this option defaults to 1, and calls to
325 ``assert()`` are left in place. For release builds, this option defaults to 0
326 and calls to ``assert()`` function are compiled out. This option can be set
327 independently of ``DEBUG``. It can also be used to hide any auxiliary code
328 that is only required for the assertion and does not fit in the assertion
329 itself.
330
331- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
332 Measurement Framework(PMF). Default is 0.
333
334- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
335 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
336 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
337 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
338 software.
339
340- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
341 instrumentation which injects timestamp collection points into
342 Trusted Firmware to allow runtime performance to be measured.
343 Currently, only PSCI is instrumented. Enabling this option enables
344 the ``ENABLE_PMF`` build option as well. Default is 0.
345
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100346- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
347 extensions. This is an optional architectural feature available only for
348 AArch64 8.2 onwards. This option defaults to 1 but is automatically
349 disabled when the target architecture is AArch32 or AArch64 8.0/8.1.
350
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100351- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
352 checks in GCC. Allowed values are "all", "strong" and "0" (default).
353 "strong" is the recommended stack protection level if this feature is
354 desired. 0 disables the stack protection. For all values other than 0, the
355 ``plat_get_stack_protector_canary()`` platform hook needs to be implemented.
356 The value is passed as the last component of the option
357 ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
358
359- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
360 deprecated platform APIs, helper functions or drivers within Trusted
361 Firmware as error. It can take the value 1 (flag the use of deprecated
362 APIs as error) or 0. The default is 0.
363
364- ``FIP_NAME``: This is an optional build option which specifies the FIP
365 filename for the ``fip`` target. Default is ``fip.bin``.
366
367- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
368 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
369
370- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
371 tool to create certificates as per the Chain of Trust described in
372 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
373 include the certificates in the FIP and FWU\_FIP. Default value is '0'.
374
375 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
376 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
377 the corresponding certificates, and to include those certificates in the
378 FIP and FWU\_FIP.
379
380 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
381 images will not include support for Trusted Board Boot. The FIP will still
382 include the corresponding certificates. This FIP can be used to verify the
383 Chain of Trust on the host machine through other mechanisms.
384
385 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
386 images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
387 will not include the corresponding certificates, causing a boot failure.
388
389- ``HANDLE_EA_EL3_FIRST``: When defined External Aborts and SError Interrupts
390 will be always trapped in EL3 i.e. in BL31 at runtime.
391
392- ``HW_ASSISTED_COHERENCY``: On most ARM systems to-date, platform-specific
393 software operations are required for CPUs to enter and exit coherency.
394 However, there exists newer systems where CPUs' entry to and exit from
395 coherency is managed in hardware. Such systems require software to only
396 initiate the operations, and the rest is managed in hardware, minimizing
397 active software management. In such systems, this boolean option enables ARM
398 Trusted Firmware to carry out build and run-time optimizations during boot
399 and power management operations. This option defaults to 0 and if it is
400 enabled, then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
401
402- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
403 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
404 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
405 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
406 images.
407
408- ``LDFLAGS``: Extra user options appended to the linkers' command line in
409 addition to the one set by the build system.
410
411- ``LOAD_IMAGE_V2``: Boolean option to enable support for new version (v2) of
412 image loading, which provides more flexibility and scalability around what
413 images are loaded and executed during boot. Default is 0.
414 Note: ``TRUSTED_BOARD_BOOT`` is currently only supported for AArch64 when
415 ``LOAD_IMAGE_V2`` is enabled.
416
417- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
418 output compiled into the build. This should be one of the following:
419
420 ::
421
422 0 (LOG_LEVEL_NONE)
423 10 (LOG_LEVEL_NOTICE)
424 20 (LOG_LEVEL_ERROR)
425 30 (LOG_LEVEL_WARNING)
426 40 (LOG_LEVEL_INFO)
427 50 (LOG_LEVEL_VERBOSE)
428
429 All log output up to and including the log level is compiled into the build.
430 The default value is 40 in debug builds and 20 in release builds.
431
432- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
433 specifies the file that contains the Non-Trusted World private key in PEM
434 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
435
436- ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
437 optional. It is only needed if the platform makefile specifies that it
438 is required in order to build the ``fwu_fip`` target.
439
440- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
441 contents upon world switch. It can take either 0 (don't save and restore) or
442 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
443 wants the timer registers to be saved and restored.
444
445- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
446 the underlying hardware is not a full PL011 UART but a minimally compliant
447 generic UART, which is a subset of the PL011. The driver will not access
448 any register that is not part of the SBSA generic UART specification.
449 Default value is 0 (a full PL011 compliant UART is present).
450
451- ``PLAT``: Choose a platform to build ARM Trusted Firmware for. The chosen
452 platform name must be subdirectory of any depth under ``plat/``, and must
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +0100453 contain a platform makefile named ``platform.mk``. For example to build ARM
454 Trusted Firmware for ARM Juno board select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100455
456- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
457 instead of the normal boot flow. When defined, it must specify the entry
458 point address for the preloaded BL33 image. This option is incompatible with
459 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
460 over ``PRELOADED_BL33_BASE``.
461
462- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
463 vector address can be programmed or is fixed on the platform. It can take
464 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
465 programmable reset address, it is expected that a CPU will start executing
466 code directly at the right address, both on a cold and warm reset. In this
467 case, there is no need to identify the entrypoint on boot and the boot path
468 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
469 does not need to be implemented in this case.
470
471- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
472 possible for the PSCI power-state parameter viz original and extended
473 State-ID formats. This flag if set to 1, configures the generic PSCI layer
474 to use the extended format. The default value of this flag is 0, which
475 means by default the original power-state format is used by the PSCI
476 implementation. This flag should be specified by the platform makefile
477 and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
478 smc function id. When this option is enabled on ARM platforms, the
479 option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.
480
481- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
482 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
483 entrypoint) or 1 (CPU reset to BL31 entrypoint).
484 The default value is 0.
485
486- ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided in
487 ARM Trusted Firmware. This flag configures SP\_MIN entrypoint as the CPU
488 reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU
489 reset to BL1 entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default
490 value is 0.
491
492- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
493 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
494 file name will be used to save the key.
495
496- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
497 certificate generation tool to save the keys used to establish the Chain of
498 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
499
500- ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
501 If a SCP\_BL2 image is present then this option must be passed for the ``fip``
502 target.
503
504- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
505 file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
506 this file name will be used to save the key.
507
508- ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
509 optional. It is only needed if the platform makefile specifies that it
510 is required in order to build the ``fwu_fip`` target.
511
512- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
513 isolated on separate memory pages. This is a trade-off between security and
514 memory usage. See "Isolating code and read-only data on separate memory
515 pages" section in `Firmware Design`_. This flag is disabled by default and
516 affects all BL images.
517
518- ``SPD``: Choose a Secure Payload Dispatcher component to be built into the
519 Trusted Firmware. This build option is only valid if ``ARCH=aarch64``. The
520 value should be the path to the directory containing the SPD source,
521 relative to ``services/spd/``; the directory is expected to
522 contain a makefile called ``<spd-value>.mk``.
523
524- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
525 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
526 execution in BL1 just before handing over to BL31. At this point, all
527 firmware images have been loaded in memory, and the MMU and caches are
528 turned off. Refer to the "Debugging options" section for more details.
529
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200530- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
531 secure interrupts (caught through the FIQ line). Platforms can enable
532 this directive if they need to handle such interruption. When enabled,
533 the FIQ are handled in monitor mode and non secure world is not allowed
534 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
535 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
536
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100537- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
538 Boot feature. When set to '1', BL1 and BL2 images include support to load
539 and verify the certificates and images in a FIP, and BL1 includes support
540 for the Firmware Update. The default value is '0'. Generation and inclusion
541 of certificates in the FIP and FWU\_FIP depends upon the value of the
542 ``GENERATE_COT`` option.
543
544 Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
545 already exist in disk, they will be overwritten without further notice.
546
547- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
548 specifies the file that contains the Trusted World private key in PEM
549 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
550
551- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
552 synchronous, (see "Initializing a BL32 Image" section in
553 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
554 synchronous method) or 1 (BL32 is initialized using asynchronous method).
555 Default is 0.
556
557- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
558 routing model which routes non-secure interrupts asynchronously from TSP
559 to EL3 causing immediate preemption of TSP. The EL3 is responsible
560 for saving and restoring the TSP context in this routing model. The
561 default routing model (when the value is 0) is to route non-secure
562 interrupts to TSP allowing it to save its context and hand over
563 synchronously to EL3 via an SMC.
564
565- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
566 memory region in the BL memory map or not (see "Use of Coherent memory in
567 Trusted Firmware" section in `Firmware Design`_). It can take the value 1
568 (Coherent memory region is included) or 0 (Coherent memory region is
569 excluded). Default is 1.
570
571- ``V``: Verbose build. If assigned anything other than 0, the build commands
572 are printed. Default is 0.
573
574- ``VERSION_STRING``: String used in the log output for each TF image. Defaults
575 to a string formed by concatenating the version number, build type and build
576 string.
577
578- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
579 the CPU after warm boot. This is applicable for platforms which do not
580 require interconnect programming to enable cache coherency (eg: single
581 cluster platforms). If this option is enabled, then warm boot path
582 enables D-caches immediately after enabling MMU. This option defaults to 0.
583
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100584ARM development platform specific build options
585^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
586
587- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
588 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
589 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
590 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
591 flag.
592
593- ``ARM_BOARD_OPTIMISE_MEM``: Boolean option to enable or disable optimisation
594 of the memory reserved for each image. This affects the maximum size of each
595 BL image as well as the number of allocated memory regions and translation
596 tables. By default this flag is 0, which means it uses the default
597 unoptimised values for these macros. ARM development platforms that wish to
598 optimise memory usage need to set this flag to 1 and must override the
599 related macros.
600
601- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
602 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
603 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
604 match the frame used by the Non-Secure image (normally the Linux kernel).
605 Default is true (access to the frame is allowed).
606
607- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
608 By default, ARM platforms use a watchdog to trigger a system reset in case
609 an error is encountered during the boot process (for example, when an image
610 could not be loaded or authenticated). The watchdog is enabled in the early
611 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
612 Trusted Watchdog may be disabled at build time for testing or development
613 purposes.
614
615- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
616 for the construction of composite state-ID in the power-state parameter.
617 The existing PSCI clients currently do not support this encoding of
618 State-ID yet. Hence this flag is used to configure whether to use the
619 recommended State-ID encoding or not. The default value of this flag is 0,
620 in which case the platform is configured to expect NULL in the State-ID
621 field of power-state parameter.
622
623- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
624 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
625 for ARM platforms. Depending on the selected option, the proper private key
626 must be specified using the ``ROT_KEY`` option when building the Trusted
627 Firmware. This private key will be used by the certificate generation tool
628 to sign the BL2 and Trusted Key certificates. Available options for
629 ``ARM_ROTPK_LOCATION`` are:
630
631 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
632 registers. The private key corresponding to this ROTPK hash is not
633 currently available.
634 - ``devel_rsa`` : return a development public key hash embedded in the BL1
635 and BL2 binaries. This hash has been obtained from the RSA public key
636 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
637 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
638 creating the certificates.
639
640- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
641
642 - ``tsram`` : Trusted SRAM (default option)
643 - ``tdram`` : Trusted DRAM (if available)
644 - ``dram`` : Secure region in DRAM (configured by the TrustZone controller)
645
646- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile the Trusted Firmware
647 with version 1 of the translation tables library instead of version 2. It is
648 set to 0 by default, which selects version 2.
649
650- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable Trusted Firmware to invoke
651 ARM® TrustZone® CryptoCell functionality for Trusted Board Boot on capable
652 ARM platforms. If this option is specified, then the path to the CryptoCell
653 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
654
655For a better understanding of these options, the ARM development platform memory
656map is explained in the `Firmware Design`_.
657
658ARM CSS platform specific build options
659^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
660
661- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
662 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
663 compatible change to the MTL protocol, used for AP/SCP communication.
664 Trusted Firmware no longer supports earlier SCP versions. If this option is
665 set to 1 then Trusted Firmware will detect if an earlier version is in use.
666 Default is 1.
667
668- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and
669 SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
670 during boot. Default is 1.
671
672- ``CSS_USE_SCMI_DRIVER``: Boolean flag which selects SCMI driver instead of
673 SCPI driver for communicating with the SCP during power management operations.
674 If this option is set to 1, then SCMI driver will be used. Default is 0.
675
676ARM FVP platform specific build options
677^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
678
679- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
680 build the topology tree within Trusted Firmware. By default the
681 Trusted Firmware is configured for dual cluster topology and this option
682 can be used to override the default value.
683
684- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
685 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
686 explained in the options below:
687
688 - ``FVP_CCI`` : The CCI driver is selected. This is the default
689 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
690 - ``FVP_CCN`` : The CCN driver is selected. This is the default
691 if ``FVP_CLUSTER_COUNT`` > 2.
692
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000693- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
694 in the system. This option defaults to 1. Note that the build option
695 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
696
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100697- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
698
699 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
700 - ``FVP_GICV2`` : The GICv2 only driver is selected
701 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
702 - ``FVP_GICV3_LEGACY``: The Legacy GICv3 driver is selected (deprecated)
703 Note: If Trusted Firmware is compiled with this option on FVPs with
704 GICv3 hardware, then it configures the hardware to run in GICv2
705 emulation mode
706
707- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
708 for functions that wait for an arbitrary time length (udelay and mdelay).
709 The default value is 0.
710
711Debugging options
712~~~~~~~~~~~~~~~~~
713
714To compile a debug version and make the build more verbose use
715
716::
717
718 make PLAT=<platform> DEBUG=1 V=1 all
719
720AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
721example DS-5) might not support this and may need an older version of DWARF
722symbols to be emitted by GCC. This can be achieved by using the
723``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
724version to 2 is recommended for DS-5 versions older than 5.16.
725
726When debugging logic problems it might also be useful to disable all compiler
727optimizations by using ``-O0``.
728
729NOTE: Using ``-O0`` could cause output images to be larger and base addresses
730might need to be recalculated (see the **Memory layout on ARM development
731platforms** section in the `Firmware Design`_).
732
733Extra debug options can be passed to the build system by setting ``CFLAGS`` or
734``LDFLAGS``:
735
736.. code:: makefile
737
738 CFLAGS='-O0 -gdwarf-2' \
739 make PLAT=<platform> DEBUG=1 V=1 all
740
741Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
742ignored as the linker is called directly.
743
744It is also possible to introduce an infinite loop to help in debugging the
745post-BL2 phase of the Trusted Firmware. This can be done by rebuilding BL1 with
Douglas Raillard30d7b362017-06-28 16:14:55 +0100746the ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100747section. In this case, the developer may take control of the target using a
748debugger when indicated by the console output. When using DS-5, the following
749commands can be used:
750
751::
752
753 # Stop target execution
754 interrupt
755
756 #
757 # Prepare your debugging environment, e.g. set breakpoints
758 #
759
760 # Jump over the debug loop
761 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
762
763 # Resume execution
764 continue
765
766Building the Test Secure Payload
767~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
768
769The TSP is coupled with a companion runtime service in the BL31 firmware,
770called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
771must be recompiled as well. For more information on SPs and SPDs, see the
772`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
773
774First clean the Trusted Firmware build directory to get rid of any previous
775BL31 binary. Then to build the TSP image use:
776
777::
778
779 make PLAT=<platform> SPD=tspd all
780
781An additional boot loader binary file is created in the ``build`` directory:
782
783::
784
785 build/<platform>/<build-type>/bl32.bin
786
787Checking source code style
788~~~~~~~~~~~~~~~~~~~~~~~~~~
789
790When making changes to the source for submission to the project, the source
791must be in compliance with the Linux style guide, and to assist with this check
792the project Makefile contains two targets, which both utilise the
793``checkpatch.pl`` script that ships with the Linux source tree.
794
795To check the entire source tree, you must first download a copy of
796``checkpatch.pl`` (or the full Linux source), set the ``CHECKPATCH`` environment
797variable to point to the script and build the target checkcodebase:
798
799::
800
801 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
802
803To just check the style on the files that differ between your local branch and
804the remote master, use:
805
806::
807
808 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
809
810If you wish to check your patch against something other than the remote master,
811set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
812is set to ``origin/master``.
813
814Building and using the FIP tool
815~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
816
817Firmware Image Package (FIP) is a packaging format used by the Trusted Firmware
818project to package firmware images in a single binary. The number and type of
819images that should be packed in a FIP is platform specific and may include TF
820images and other firmware images required by the platform. For example, most
821platforms require a BL33 image which corresponds to the normal world bootloader
822(e.g. UEFI or U-Boot).
823
824The TF build system provides the make target ``fip`` to create a FIP file for the
825specified platform using the FIP creation tool included in the TF project.
826Examples below show how to build a FIP file for FVP, packaging TF images and a
827BL33 image.
828
829For AArch64:
830
831::
832
833 make PLAT=fvp BL33=<path/to/bl33.bin> fip
834
835For AArch32:
836
837::
838
839 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip
840
841Note that AArch32 support for Normal world boot loader (BL33), like U-boot or
842UEFI, on FVP is not available upstream. Hence custom solutions are required to
843allow Linux boot on FVP. These instructions assume such a custom boot loader
844(BL33) is available.
845
846The resulting FIP may be found in:
847
848::
849
850 build/fvp/<build-type>/fip.bin
851
852For advanced operations on FIP files, it is also possible to independently build
853the tool and create or modify FIPs using this tool. To do this, follow these
854steps:
855
856It is recommended to remove old artifacts before building the tool:
857
858::
859
860 make -C tools/fiptool clean
861
862Build the tool:
863
864::
865
866 make [DEBUG=1] [V=1] fiptool
867
868The tool binary can be located in:
869
870::
871
872 ./tools/fiptool/fiptool
873
874Invoking the tool with ``--help`` will print a help message with all available
875options.
876
877Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
878
879::
880
881 ./tools/fiptool/fiptool create \
882 --tb-fw build/<platform>/<build-type>/bl2.bin \
883 --soc-fw build/<platform>/<build-type>/bl31.bin \
884 fip.bin
885
886Example 2: view the contents of an existing Firmware package:
887
888::
889
890 ./tools/fiptool/fiptool info <path-to>/fip.bin
891
892Example 3: update the entries of an existing Firmware package:
893
894::
895
896 # Change the BL2 from Debug to Release version
897 ./tools/fiptool/fiptool update \
898 --tb-fw build/<platform>/release/bl2.bin \
899 build/<platform>/debug/fip.bin
900
901Example 4: unpack all entries from an existing Firmware package:
902
903::
904
905 # Images will be unpacked to the working directory
906 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
907
908Example 5: remove an entry from an existing Firmware package:
909
910::
911
912 ./tools/fiptool/fiptool remove \
913 --tb-fw build/<platform>/debug/fip.bin
914
915Note that if the destination FIP file exists, the create, update and
916remove operations will automatically overwrite it.
917
918The unpack operation will fail if the images already exist at the
919destination. In that case, use -f or --force to continue.
920
921More information about FIP can be found in the `Firmware Design`_ document.
922
923Migrating from fip\_create to fiptool
924^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
925
926The previous version of fiptool was called fip\_create. A compatibility script
927that emulates the basic functionality of the previous fip\_create is provided.
928However, users are strongly encouraged to migrate to fiptool.
929
930- To create a new FIP file, replace "fip\_create" with "fiptool create".
931- To update a FIP file, replace "fip\_create" with "fiptool update".
932- To dump the contents of a FIP file, replace "fip\_create --dump"
933 with "fiptool info".
934
935Building FIP images with support for Trusted Board Boot
936~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
937
938Trusted Board Boot primarily consists of the following two features:
939
940- Image Authentication, described in `Trusted Board Boot`_, and
941- Firmware Update, described in `Firmware Update`_
942
943The following steps should be followed to build FIP and (optionally) FWU\_FIP
944images with support for these features:
945
946#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
947 modules by checking out a recent version of the `mbed TLS Repository`_. It
948 is important to use a version that is compatible with TF and fixes any
949 known security vulnerabilities. See `mbed TLS Security Center`_ for more
950 information. The latest version of TF is tested with tag ``mbedtls-2.4.2``.
951
952 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
953 source files the modules depend upon.
954 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
955 options required to build the mbed TLS sources.
956
957 Note that the mbed TLS library is licensed under the Apache version 2.0
958 license. Using mbed TLS source code will affect the licensing of
959 Trusted Firmware binaries that are built using this library.
960
961#. To build the FIP image, ensure the following command line variables are set
962 while invoking ``make`` to build Trusted Firmware:
963
964 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
965 - ``TRUSTED_BOARD_BOOT=1``
966 - ``GENERATE_COT=1``
967
968 In the case of ARM platforms, the location of the ROTPK hash must also be
969 specified at build time. Two locations are currently supported (see
970 ``ARM_ROTPK_LOCATION`` build option):
971
972 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
973 root-key storage registers present in the platform. On Juno, this
974 registers are read-only. On FVP Base and Cortex models, the registers
975 are read-only, but the value can be specified using the command line
976 option ``bp.trusted_key_storage.public_key`` when launching the model.
977 On both Juno and FVP models, the default value corresponds to an
978 ECDSA-SECP256R1 public key hash, whose private part is not currently
979 available.
980
981 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
982 in the ARM platform port. The private/public RSA key pair may be
983 found in ``plat/arm/board/common/rotpk``.
984
985 Example of command line using RSA development keys:
986
987 ::
988
989 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
990 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
991 ARM_ROTPK_LOCATION=devel_rsa \
992 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
993 BL33=<path-to>/<bl33_image> \
994 all fip
995
996 The result of this build will be the bl1.bin and the fip.bin binaries. This
997 FIP will include the certificates corresponding to the Chain of Trust
998 described in the TBBR-client document. These certificates can also be found
999 in the output build directory.
1000
1001#. The optional FWU\_FIP contains any additional images to be loaded from
1002 Non-Volatile storage during the `Firmware Update`_ process. To build the
1003 FWU\_FIP, any FWU images required by the platform must be specified on the
1004 command line. On ARM development platforms like Juno, these are:
1005
1006 - NS\_BL2U. The AP non-secure Firmware Updater image.
1007 - SCP\_BL2U. The SCP Firmware Update Configuration image.
1008
1009 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1010 targets using RSA development:
1011
1012 ::
1013
1014 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1015 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1016 ARM_ROTPK_LOCATION=devel_rsa \
1017 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1018 BL33=<path-to>/<bl33_image> \
1019 SCP_BL2=<path-to>/<scp_bl2_image> \
1020 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1021 NS_BL2U=<path-to>/<ns_bl2u_image> \
1022 all fip fwu_fip
1023
1024 Note: The BL2U image will be built by default and added to the FWU\_FIP.
1025 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1026 to the command line above.
1027
1028 Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
1029 NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
1030
1031 The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries.
1032 Both the FIP and FWU\_FIP will include the certificates corresponding to the
1033 Chain of Trust described in the TBBR-client document. These certificates
1034 can also be found in the output build directory.
1035
1036Building the Certificate Generation Tool
1037~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1038
1039The ``cert_create`` tool is built as part of the TF build process when the ``fip``
1040make target is specified and TBB is enabled (as described in the previous
1041section), but it can also be built separately with the following command:
1042
1043::
1044
1045 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1046
1047For platforms that do not require their own IDs in certificate files,
1048the generic 'cert\_create' tool can be built with the following command:
1049
1050::
1051
1052 make USE_TBBR_DEFS=1 [DEBUG=1] [V=1] certtool
1053
1054``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1055verbose. The following command should be used to obtain help about the tool:
1056
1057::
1058
1059 ./tools/cert_create/cert_create -h
1060
1061Building a FIP for Juno and FVP
1062-------------------------------
1063
1064This section provides Juno and FVP specific instructions to build Trusted
1065Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001066a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001067
David Cunadob2de0992017-06-29 12:01:33 +01001068Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
1069onwards. Before that release, pre-built binaries are only available for AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001070
1071Note: follow the full instructions for one platform before switching to a
1072different one. Mixing instructions for different platforms may result in
1073corrupted binaries.
1074
1075#. Clean the working directory
1076
1077 ::
1078
1079 make realclean
1080
1081#. Obtain SCP\_BL2 (Juno) and BL33 (all platforms)
1082
1083 Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
1084 package included in the Linaro release:
1085
1086 ::
1087
1088 # Build the fiptool
1089 make [DEBUG=1] [V=1] fiptool
1090
1091 # Unpack firmware images from Linaro FIP
1092 ./tools/fiptool/fiptool unpack \
1093 <path/to/linaro/release>/fip.bin
1094
1095 The unpack operation will result in a set of binary images extracted to the
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001096 current working directory. The SCP\_BL2 image corresponds to
1097 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001098
1099 Note: the fiptool will complain if the images to be unpacked already
1100 exist in the current directory. If that is the case, either delete those
1101 files or use the ``--force`` option to overwrite.
1102
1103 Note for AArch32, the instructions below assume that nt-fw.bin is a custom
1104 Normal world boot loader that supports AArch32.
1105
1106#. Build TF images and create a new FIP for FVP
1107
1108 ::
1109
1110 # AArch64
1111 make PLAT=fvp BL33=nt-fw.bin all fip
1112
1113 # AArch32
1114 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1115
1116#. Build TF images and create a new FIP for Juno
1117
1118 For AArch64:
1119
1120 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1121 as a build parameter.
1122
1123 ::
1124
1125 make PLAT=juno all fip \
1126 BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \
1127 SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin
1128
1129 For AArch32:
1130
1131 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1132 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1133 separately for AArch32.
1134
1135 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1136 to the AArch32 Linaro cross compiler.
1137
1138 ::
1139
1140 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1141
1142 - Build BL32 in AArch32.
1143
1144 ::
1145
1146 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1147 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1148
1149 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1150 must point to the AArch64 Linaro cross compiler.
1151
1152 ::
1153
1154 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1155
1156 - The following parameters should be used to build BL1 and BL2 in AArch64
1157 and point to the BL32 file.
1158
1159 ::
1160
1161 make ARCH=aarch64 PLAT=juno LOAD_IMAGE_V2=1 JUNO_AARCH32_EL3_RUNTIME=1 \
1162 BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
1163 SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin SPD=tspd \
1164 BL32=<path-to-bl32>/bl32.bin all fip
1165
1166The resulting BL1 and FIP images may be found in:
1167
1168::
1169
1170 # Juno
1171 ./build/juno/release/bl1.bin
1172 ./build/juno/release/fip.bin
1173
1174 # FVP
1175 ./build/fvp/release/bl1.bin
1176 ./build/fvp/release/fip.bin
1177
1178EL3 payloads alternative boot flow
1179----------------------------------
1180
1181On a pre-production system, the ability to execute arbitrary, bare-metal code at
1182the highest exception level is required. It allows full, direct access to the
1183hardware, for example to run silicon soak tests.
1184
1185Although it is possible to implement some baremetal secure firmware from
1186scratch, this is a complex task on some platforms, depending on the level of
1187configuration required to put the system in the expected state.
1188
1189Rather than booting a baremetal application, a possible compromise is to boot
1190``EL3 payloads`` through the Trusted Firmware instead. This is implemented as an
1191alternative boot flow, where a modified BL2 boots an EL3 payload, instead of
1192loading the other BL images and passing control to BL31. It reduces the
1193complexity of developing EL3 baremetal code by:
1194
1195- putting the system into a known architectural state;
1196- taking care of platform secure world initialization;
1197- loading the SCP\_BL2 image if required by the platform.
1198
1199When booting an EL3 payload on ARM standard platforms, the configuration of the
1200TrustZone controller is simplified such that only region 0 is enabled and is
1201configured to permit secure access only. This gives full access to the whole
1202DRAM to the EL3 payload.
1203
1204The system is left in the same state as when entering BL31 in the default boot
1205flow. In particular:
1206
1207- Running in EL3;
1208- Current state is AArch64;
1209- Little-endian data access;
1210- All exceptions disabled;
1211- MMU disabled;
1212- Caches disabled.
1213
1214Booting an EL3 payload
1215~~~~~~~~~~~~~~~~~~~~~~
1216
1217The EL3 payload image is a standalone image and is not part of the FIP. It is
1218not loaded by the Trusted Firmware. Therefore, there are 2 possible scenarios:
1219
1220- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1221 place. In this case, booting it is just a matter of specifying the right
1222 address in NVM through ``EL3_PAYLOAD_BASE`` when building the TF.
1223
1224- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1225 run-time.
1226
1227To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1228used. The infinite loop that it introduces in BL1 stops execution at the right
1229moment for a debugger to take control of the target and load the payload (for
1230example, over JTAG).
1231
1232It is expected that this loading method will work in most cases, as a debugger
1233connection is usually available in a pre-production system. The user is free to
1234use any other platform-specific mechanism to load the EL3 payload, though.
1235
1236Booting an EL3 payload on FVP
1237^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1238
1239The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1240the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1241is undefined on the FVP platform and the FVP platform code doesn't clear it.
1242Therefore, one must modify the way the model is normally invoked in order to
1243clear the mailbox at start-up.
1244
1245One way to do that is to create an 8-byte file containing all zero bytes using
1246the following command:
1247
1248::
1249
1250 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1251
1252and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1253using the following model parameters:
1254
1255::
1256
1257 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1258 --data=mailbox.dat@0x04000000 [Foundation FVP]
1259
1260To provide the model with the EL3 payload image, the following methods may be
1261used:
1262
1263#. If the EL3 payload is able to execute in place, it may be programmed into
1264 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1265 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1266 used for the FIP):
1267
1268 ::
1269
1270 -C bp.flashloader1.fname="/path/to/el3-payload"
1271
1272 On Foundation FVP, there is no flash loader component and the EL3 payload
1273 may be programmed anywhere in flash using method 3 below.
1274
1275#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1276 command may be used to load the EL3 payload ELF image over JTAG:
1277
1278 ::
1279
1280 load /path/to/el3-payload.elf
1281
1282#. The EL3 payload may be pre-loaded in volatile memory using the following
1283 model parameters:
1284
1285 ::
1286
1287 --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs]
1288 --data="/path/to/el3-payload"@address [Foundation FVP]
1289
1290 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
1291 used when building the Trusted Firmware.
1292
1293Booting an EL3 payload on Juno
1294^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1295
1296If the EL3 payload is able to execute in place, it may be programmed in flash
1297memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1298on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1299Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1300programming" for more information.
1301
1302Alternatively, the same DS-5 command mentioned in the FVP section above can
1303be used to load the EL3 payload's ELF file over JTAG on Juno.
1304
1305Preloaded BL33 alternative boot flow
1306------------------------------------
1307
1308Some platforms have the ability to preload BL33 into memory instead of relying
1309on Trusted Firmware to load it. This may simplify packaging of the normal world
1310code and improve performance in a development environment. When secure world
1311cold boot is complete, Trusted Firmware simply jumps to a BL33 base address
1312provided at build time.
1313
1314For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
1315used when compiling the Trusted Firmware. For example, the following command
1316will create a FIP without a BL33 and prepare to jump to a BL33 image loaded at
1317address 0x80000000:
1318
1319::
1320
1321 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1322
1323Boot of a preloaded bootwrapped kernel image on Base FVP
1324~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1325
1326The following example uses the AArch64 boot wrapper. This simplifies normal
1327world booting while also making use of TF features. It can be obtained from its
1328repository with:
1329
1330::
1331
1332 git clone git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git
1333
1334After compiling it, an ELF file is generated. It can be loaded with the
1335following command:
1336
1337::
1338
1339 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1340 -C bp.secureflashloader.fname=bl1.bin \
1341 -C bp.flashloader0.fname=fip.bin \
1342 -a cluster0.cpu0=<bootwrapped-kernel.elf> \
1343 --start cluster0.cpu0=0x0
1344
1345The ``-a cluster0.cpu0=<bootwrapped-kernel.elf>`` option loads the ELF file. It
1346also sets the PC register to the ELF entry point address, which is not the
1347desired behaviour, so the ``--start cluster0.cpu0=0x0`` option forces the PC back
1348to 0x0 (the BL1 entry point address) on CPU #0. The ``PRELOADED_BL33_BASE`` define
1349used when compiling the FIP must match the ELF entry point.
1350
1351Boot of a preloaded bootwrapped kernel image on Juno
1352~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1353
1354The procedure to obtain and compile the boot wrapper is very similar to the case
1355of the FVP. The execution must be stopped at the end of bl2\_main(), and the
1356loading method explained above in the EL3 payload boot flow section may be used
1357to load the ELF file over JTAG on Juno.
1358
1359Running the software on FVP
1360---------------------------
1361
1362The latest version of the AArch64 build of ARM Trusted Firmware has been tested
1363on the following ARM FVPs (64-bit host machine only).
1364
David Cunado124415e2017-06-27 17:31:12 +01001365NOTE: Unless otherwise stated, the model version is Version 11.0 Build 11.0.34.
1366
1367- ``Foundation_Platform``
1368- ``FVP_Base_AEMv8A-AEMv8A`` (Version 8.5, Build 0.8.8502)
1369- ``FVP_Base_Cortex-A35x4``
1370- ``FVP_Base_Cortex-A53x4``
1371- ``FVP_Base_Cortex-A57x4-A53x4``
1372- ``FVP_Base_Cortex-A57x4``
1373- ``FVP_Base_Cortex-A72x4-A53x4``
1374- ``FVP_Base_Cortex-A72x4``
1375- ``FVP_Base_Cortex-A73x4-A53x4``
1376- ``FVP_Base_Cortex-A73x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001377
1378The latest version of the AArch32 build of ARM Trusted Firmware has been tested
1379on the following ARM FVPs (64-bit host machine only).
1380
David Cunado124415e2017-06-27 17:31:12 +01001381- ``FVP_Base_AEMv8A-AEMv8A`` (Version 8.5, Build 0.8.8502)
1382- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001383
1384NOTE: The build numbers quoted above are those reported by launching the FVP
1385with the ``--version`` parameter.
1386
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001387NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full
1388file systems that can be downloaded separately. To run an FVP with a virtio
1389file system image an additional FVP configuration option
1390``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1391used.
1392
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001393NOTE: The software will not work on Version 1.0 of the Foundation FVP.
1394The commands below would report an ``unhandled argument`` error in this case.
1395
1396NOTE: FVPs can be launched with ``--cadi-server`` option such that a
1397CADI-compliant debugger (for example, ARM DS-5) can connect to and control its
1398execution.
1399
1400The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
1401downloaded for free from `ARM's website`_.
1402
David Cunado124415e2017-06-27 17:31:12 +01001403The Cortex-A models listed above are also available to download from
1404`ARM's website`_.
1405
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001406Please refer to the FVP documentation for a detailed description of the model
1407parameter options. A brief description of the important ones that affect the ARM
1408Trusted Firmware and normal world software behavior is provided below.
1409
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001410Obtaining the Flattened Device Trees
1411~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1412
1413Depending on the FVP configuration and Linux configuration used, different
1414FDT files are required. FDTs for the Foundation and Base FVPs can be found in
1415the Trusted Firmware source directory under ``fdts/``. The Foundation FVP has a
1416subset of the Base FVP components. For example, the Foundation FVP lacks CLCD
1417and MMC support, and has only one CPU cluster.
1418
1419Note: It is not recommended to use the FDTs built along the kernel because not
1420all FDTs are available from there.
1421
1422- ``fvp-base-gicv2-psci.dtb``
1423
1424 For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
1425 Base memory map configuration.
1426
1427- ``fvp-base-gicv2-psci-aarch32.dtb``
1428
1429 For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state
1430 with Base memory map configuration.
1431
1432- ``fvp-base-gicv3-psci.dtb``
1433
1434 (Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base
1435 memory map configuration and Linux GICv3 support.
1436
1437- ``fvp-base-gicv3-psci-aarch32.dtb``
1438
1439 For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state
1440 with Base memory map configuration and Linux GICv3 support.
1441
1442- ``fvp-foundation-gicv2-psci.dtb``
1443
1444 For use with Foundation FVP with Base memory map configuration.
1445
1446- ``fvp-foundation-gicv3-psci.dtb``
1447
1448 (Default) For use with Foundation FVP with Base memory map configuration
1449 and Linux GICv3 support.
1450
1451Running on the Foundation FVP with reset to BL1 entrypoint
1452~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1453
1454The following ``Foundation_Platform`` parameters should be used to boot Linux with
14554 CPUs using the AArch64 build of ARM Trusted Firmware.
1456
1457::
1458
1459 <path-to>/Foundation_Platform \
1460 --cores=4 \
1461 --secure-memory \
1462 --visualization \
1463 --gicv3 \
1464 --data="<path-to>/<bl1-binary>"@0x0 \
1465 --data="<path-to>/<FIP-binary>"@0x08000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001466 --data="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001467 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001468 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001469
1470Notes:
1471
1472- BL1 is loaded at the start of the Trusted ROM.
1473- The Firmware Image Package is loaded at the start of NOR FLASH0.
1474- The Linux kernel image and device tree are loaded in DRAM.
1475- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1476 and enable the GICv3 device in the model. Note that without this option,
1477 the Foundation FVP defaults to legacy (Versatile Express) memory map which
1478 is not supported by ARM Trusted Firmware.
1479
1480Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1481~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1482
1483The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1484with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1485
1486::
1487
1488 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1489 -C pctl.startup=0.0.0.0 \
1490 -C bp.secure_memory=1 \
1491 -C bp.tzc_400.diagnostics=1 \
1492 -C cluster0.NUM_CORES=4 \
1493 -C cluster1.NUM_CORES=4 \
1494 -C cache_state_modelled=1 \
1495 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1496 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001497 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001498 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001499 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001500
1501Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1502~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1503
1504The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1505with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
1506
1507::
1508
1509 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1510 -C pctl.startup=0.0.0.0 \
1511 -C bp.secure_memory=1 \
1512 -C bp.tzc_400.diagnostics=1 \
1513 -C cluster0.NUM_CORES=4 \
1514 -C cluster1.NUM_CORES=4 \
1515 -C cache_state_modelled=1 \
1516 -C cluster0.cpu0.CONFIG64=0 \
1517 -C cluster0.cpu1.CONFIG64=0 \
1518 -C cluster0.cpu2.CONFIG64=0 \
1519 -C cluster0.cpu3.CONFIG64=0 \
1520 -C cluster1.cpu0.CONFIG64=0 \
1521 -C cluster1.cpu1.CONFIG64=0 \
1522 -C cluster1.cpu2.CONFIG64=0 \
1523 -C cluster1.cpu3.CONFIG64=0 \
1524 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1525 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001526 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001527 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001528 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001529
1530Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1531~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1532
1533The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
1534boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1535
1536::
1537
1538 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1539 -C pctl.startup=0.0.0.0 \
1540 -C bp.secure_memory=1 \
1541 -C bp.tzc_400.diagnostics=1 \
1542 -C cache_state_modelled=1 \
1543 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1544 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001545 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001546 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001547 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001548
1549Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1550~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1551
1552The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
1553boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
1554
1555::
1556
1557 <path-to>/FVP_Base_Cortex-A32x4 \
1558 -C pctl.startup=0.0.0.0 \
1559 -C bp.secure_memory=1 \
1560 -C bp.tzc_400.diagnostics=1 \
1561 -C cache_state_modelled=1 \
1562 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1563 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001564 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001565 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001566 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001567
1568Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1569~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1570
1571The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1572with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1573
1574::
1575
1576 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1577 -C pctl.startup=0.0.0.0 \
1578 -C bp.secure_memory=1 \
1579 -C bp.tzc_400.diagnostics=1 \
1580 -C cluster0.NUM_CORES=4 \
1581 -C cluster1.NUM_CORES=4 \
1582 -C cache_state_modelled=1 \
1583 -C cluster0.cpu0.RVBAR=0x04023000 \
1584 -C cluster0.cpu1.RVBAR=0x04023000 \
1585 -C cluster0.cpu2.RVBAR=0x04023000 \
1586 -C cluster0.cpu3.RVBAR=0x04023000 \
1587 -C cluster1.cpu0.RVBAR=0x04023000 \
1588 -C cluster1.cpu1.RVBAR=0x04023000 \
1589 -C cluster1.cpu2.RVBAR=0x04023000 \
1590 -C cluster1.cpu3.RVBAR=0x04023000 \
1591 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04023000 \
1592 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1593 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001594 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001595 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001596 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001597
1598Notes:
1599
1600- Since a FIP is not loaded when using BL31 as reset entrypoint, the
1601 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
1602 parameter is needed to load the individual bootloader images in memory.
1603 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
1604 Payload.
1605
1606- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
1607 X and Y are the cluster and CPU numbers respectively, is used to set the
1608 reset vector for each core.
1609
1610- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
1611 changing the value of
1612 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
1613 ``BL32_BASE``.
1614
1615Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1616~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1617
1618The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1619with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
1620
1621::
1622
1623 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1624 -C pctl.startup=0.0.0.0 \
1625 -C bp.secure_memory=1 \
1626 -C bp.tzc_400.diagnostics=1 \
1627 -C cluster0.NUM_CORES=4 \
1628 -C cluster1.NUM_CORES=4 \
1629 -C cache_state_modelled=1 \
1630 -C cluster0.cpu0.CONFIG64=0 \
1631 -C cluster0.cpu1.CONFIG64=0 \
1632 -C cluster0.cpu2.CONFIG64=0 \
1633 -C cluster0.cpu3.CONFIG64=0 \
1634 -C cluster1.cpu0.CONFIG64=0 \
1635 -C cluster1.cpu1.CONFIG64=0 \
1636 -C cluster1.cpu2.CONFIG64=0 \
1637 -C cluster1.cpu3.CONFIG64=0 \
1638 -C cluster0.cpu0.RVBAR=0x04001000 \
1639 -C cluster0.cpu1.RVBAR=0x04001000 \
1640 -C cluster0.cpu2.RVBAR=0x04001000 \
1641 -C cluster0.cpu3.RVBAR=0x04001000 \
1642 -C cluster1.cpu0.RVBAR=0x04001000 \
1643 -C cluster1.cpu1.RVBAR=0x04001000 \
1644 -C cluster1.cpu2.RVBAR=0x04001000 \
1645 -C cluster1.cpu3.RVBAR=0x04001000 \
1646 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1647 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001648 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001649 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001650 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001651
1652Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
1653It should match the address programmed into the RVBAR register as well.
1654
1655Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
1656~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1657
1658The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
1659boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1660
1661::
1662
1663 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1664 -C pctl.startup=0.0.0.0 \
1665 -C bp.secure_memory=1 \
1666 -C bp.tzc_400.diagnostics=1 \
1667 -C cache_state_modelled=1 \
1668 -C cluster0.cpu0.RVBARADDR=0x04023000 \
1669 -C cluster0.cpu1.RVBARADDR=0x04023000 \
1670 -C cluster0.cpu2.RVBARADDR=0x04023000 \
1671 -C cluster0.cpu3.RVBARADDR=0x04023000 \
1672 -C cluster1.cpu0.RVBARADDR=0x04023000 \
1673 -C cluster1.cpu1.RVBARADDR=0x04023000 \
1674 -C cluster1.cpu2.RVBARADDR=0x04023000 \
1675 -C cluster1.cpu3.RVBARADDR=0x04023000 \
1676 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04023000 \
1677 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1678 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001679 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001680 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001681 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001682
1683Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1684~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1685
1686The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
1687boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
1688
1689::
1690
1691 <path-to>/FVP_Base_Cortex-A32x4 \
1692 -C pctl.startup=0.0.0.0 \
1693 -C bp.secure_memory=1 \
1694 -C bp.tzc_400.diagnostics=1 \
1695 -C cache_state_modelled=1 \
1696 -C cluster0.cpu0.RVBARADDR=0x04001000 \
1697 -C cluster0.cpu1.RVBARADDR=0x04001000 \
1698 -C cluster0.cpu2.RVBARADDR=0x04001000 \
1699 -C cluster0.cpu3.RVBARADDR=0x04001000 \
1700 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1701 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001702 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001703 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001704 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001705
1706Running the software on Juno
1707----------------------------
1708
David Cunadob2de0992017-06-29 12:01:33 +01001709This version of the ARM Trusted Firmware has been tested on variants r0, r1 and
1710r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001711
1712To execute the software stack on Juno, the version of the Juno board recovery
1713image indicated in the `Linaro Release Notes`_ must be installed. If you have an
1714earlier version installed or are unsure which version is installed, please
1715re-install the recovery image by following the
1716`Instructions for using Linaro's deliverables on Juno`_.
1717
1718Preparing Trusted Firmware images
1719~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1720
1721After building Trusted Firmware, the files ``bl1.bin`` and ``fip.bin`` need copying
1722to the ``SOFTWARE/`` directory of the Juno SD card.
1723
1724Other Juno software information
1725~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1726
1727Please visit the `ARM Platforms Portal`_ to get support and obtain any other Juno
1728software information. Please also refer to the `Juno Getting Started Guide`_ to
1729get more detailed information about the Juno ARM development platform and how to
1730configure it.
1731
1732Testing SYSTEM SUSPEND on Juno
1733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1734
1735The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
1736to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
1737on Juno, at the linux shell prompt, issue the following command:
1738
1739::
1740
1741 echo +10 > /sys/class/rtc/rtc0/wakealarm
1742 echo -n mem > /sys/power/state
1743
1744The Juno board should suspend to RAM and then wakeup after 10 seconds due to
1745wakeup interrupt from RTC.
1746
1747--------------
1748
1749*Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.*
1750
David Cunadob2de0992017-06-29 12:01:33 +01001751.. _Linaro: `Linaro Release Notes`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001752.. _Linaro Release: `Linaro Release Notes`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001753.. _Linaro Release Notes: https://community.arm.com/tools/dev-platforms/b/documents/posts/linaro-release-notes-deprecated
David Cunadob2de0992017-06-29 12:01:33 +01001754.. _Linaro Release 17.04: https://community.arm.com/tools/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease17.04
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001755.. _Linaro instructions: https://community.arm.com/dev-platforms/b/documents/posts/instructions-for-using-the-linaro-software-deliverables
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001756.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/b/documents/posts/using-linaros-deliverables-on-juno
1757.. _ARM Platforms Portal: https://community.arm.com/dev-platforms/
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001758.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01001759.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001760.. _here: psci-lib-integration-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001761.. _Trusted Board Boot: trusted-board-boot.rst
1762.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001763.. _Firmware Update: firmware-update.rst
1764.. _Firmware Design: firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001765.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
1766.. _mbed TLS Security Center: https://tls.mbed.org/security
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001767.. _ARM's website: `FVP models`_
1768.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001769.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01001770.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf