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git01.mediatek.com / filogic / atf / e3cc838abcc12edbad2b4f6dda1a3d8f40c2944f / . / plat / rockchip / rk3368 / drivers / pmu / pmu.h
blob: 4c021074afd5cc8d775a0c5d7ba9abf3fef25563 [file] [log] [blame]
Tony Xief6118cc2016-01-15 17:17:32 +0800[diff] [blame]1/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +0800[diff] [blame]5 */
6
7#ifndef __PMU_H__
8#define __PMU_H__
9
10/* Allocate sp reginon in pmusram */
11#define PSRAM_SP_SIZE 0x80
12#define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE)
13
14/*****************************************************************************
15 * pmu con,reg
16 *****************************************************************************/
17#define PMU_WKUP_CFG0 0x0
18#define PMU_WKUP_CFG1 0x4
19#define PMU_WKUP_CFG2 0x8
20#define PMU_TIMEOUT_CNT 0x7c
21#define PMU_PWRDN_CON 0xc
22#define PMU_PWRDN_ST 0x10
23#define PMU_CORE_PWR_ST 0x38
24
25#define PMU_PWRMD_CORE 0x14
26#define PMU_PWRMD_COM 0x18
27#define PMU_SFT_CON 0x1c
28#define PMU_BUS_IDE_REQ 0x3c
29#define PMU_BUS_IDE_ST 0x40
30#define PMU_OSC_CNT 0x48
31#define PMU_PLLLOCK_CNT 0x4c
32#define PMU_PLLRST_CNT 0x50
33#define PMU_STABLE_CNT 0x54
34#define PMU_DDRIO_PWR_CNT 0x58
35#define PMU_WKUPRST_CNT 0x5c
36
37enum pmu_powermode_core {
38 pmu_mdcr_global_int_dis = 0,
39 pmu_mdcr_core_src_gt,
40 pmu_mdcr_clr_cci,
41 pmu_mdcr_cpu0_pd,
42 pmu_mdcr_clr_clst_l = 4,
43 pmu_mdcr_clr_core,
44 pmu_mdcr_scu_l_pd,
45 pmu_mdcr_core_pd,
46 pmu_mdcr_l2_idle = 8,
47 pmu_mdcr_l2_flush
48};
49
50/*
51 * the shift of bits for cores status
52 */
53enum pmu_core_pwrst_shift {
54 clstl_cpu_wfe = 2,
55 clstl_cpu_wfi = 6,
56 clstb_cpu_wfe = 12,
57 clstb_cpu_wfi = 16
58};
59
60enum pmu_pdid {
61 PD_CPUL0 = 0,
62 PD_CPUL1,
63 PD_CPUL2,
64 PD_CPUL3,
65 PD_SCUL,
66 PD_CPUB0 = 5,
67 PD_CPUB1,
68 PD_CPUB2,
69 PD_CPUB3,
70 PD_SCUB = 9,
71 PD_PERI = 13,
72 PD_VIDEO,
73 PD_VIO,
74 PD_GPU0,
75 PD_GPU1,
76 PD_END
77};
78
79enum pmu_bus_ide {
80 bus_ide_req_clst_l = 0,
81 bus_ide_req_clst_b,
82 bus_ide_req_gpu,
83 bus_ide_req_core,
84 bus_ide_req_bus = 4,
85 bus_ide_req_dma,
86 bus_ide_req_peri,
87 bus_ide_req_video,
88 bus_ide_req_vio = 8,
89 bus_ide_req_res0,
90 bus_ide_req_cxcs,
91 bus_ide_req_alive,
92 bus_ide_req_pmu = 12,
93 bus_ide_req_msch,
94 bus_ide_req_cci,
95 bus_ide_req_cci400 = 15,
96 bus_ide_req_end
97};
98
99enum pmu_powermode_common {
100 pmu_mode_en = 0,
101 pmu_mode_res0,
102 pmu_mode_bus_pd,
103 pmu_mode_wkup_rst,
104 pmu_mode_pll_pd = 4,
105 pmu_mode_pwr_off,
106 pmu_mode_pmu_use_if,
107 pmu_mode_pmu_alive_use_if,
108 pmu_mode_osc_dis = 8,
109 pmu_mode_input_clamp,
110 pmu_mode_sref_enter,
111 pmu_mode_ddrc_gt,
112 pmu_mode_ddrio_ret = 12,
113 pmu_mode_ddrio_ret_deq,
114 pmu_mode_clr_pmu,
115 pmu_mode_clr_alive,
116 pmu_mode_clr_bus = 16,
117 pmu_mode_clr_dma,
118 pmu_mode_clr_msch,
119 pmu_mode_clr_peri,
120 pmu_mode_clr_video = 20,
121 pmu_mode_clr_vio,
122 pmu_mode_clr_gpu,
123 pmu_mode_clr_mcu,
124 pmu_mode_clr_cxcs = 24,
125 pmu_mode_clr_cci400,
126 pmu_mode_res1,
127 pmu_mode_res2,
128 pmu_mode_res3 = 28,
129 pmu_mode_mclst
130};
131
132enum pmu_core_power_st {
133 clst_l_cpu_wfe = 2,
134 clst_l_cpu_wfi = 6,
135 clst_b_l2_flsh_done = 10,
136 clst_b_l2_wfi = 11,
137 clst_b_cpu_wfe = 12,
138 clst_b_cpu_wfi = 16,
139 mcu_sleeping = 20,
140};
141
142enum pmu_sft_con {
143 pmu_sft_acinactm_clst_b = 5,
144 pmu_sft_l2flsh_clst_b,
145 pmu_sft_glbl_int_dis_b = 9,
146 pmu_sft_ddrio_ret_cfg = 11,
147};
148
149enum pmu_wkup_cfg2 {
150 pmu_cluster_l_wkup_en = 0,
151 pmu_cluster_b_wkup_en,
152 pmu_gpio_wkup_en,
153 pmu_sdio_wkup_en,
154 pmu_sdmmc_wkup_en,
155 pmu_sim_wkup_en,
156 pmu_timer_wkup_en,
157 pmu_usbdev_wkup_en,
158 pmu_sft_wkup_en,
159 pmu_wdt_mcu_wkup_en,
160 pmu_timeout_wkup_en,
161};
162
163enum pmu_bus_idle_st {
164 pmu_idle_ack_cluster_l = 0,
165 pmu_idle_ack_cluster_b,
166 pmu_idle_ack_gpu,
167 pmu_idle_ack_core,
168 pmu_idle_ack_bus,
169 pmu_idle_ack_dma,
170 pmu_idle_ack_peri,
171 pmu_idle_ack_video,
172 pmu_idle_ack_vio,
173 pmu_idle_ack_cci = 10,
174 pmu_idle_ack_msch,
175 pmu_idle_ack_alive,
176 pmu_idle_ack_pmu,
177 pmu_idle_ack_cxcs,
178 pmu_idle_ack_cci400,
179 pmu_inactive_cluster_l,
180 pmu_inactive_cluster_b,
181 pmu_idle_gpu,
182 pmu_idle_core,
183 pmu_idle_bus,
184 pmu_idle_dma,
185 pmu_idle_peri,
186 pmu_idle_video,
187 pmu_idle_vio,
188 pmu_idle_cci = 26,
189 pmu_idle_msch,
190 pmu_idle_alive,
191 pmu_idle_pmu,
192 pmu_active_cxcs,
193 pmu_active_cci,
194};
195
196#define PM_PWRDM_CPUSB_MSK (0xf << 5)
197
198#define CKECK_WFE_MSK 0x1
199#define CKECK_WFI_MSK 0x10
200#define CKECK_WFEI_MSK 0x11
201
202#define PD_CTR_LOOP 500
203#define CHK_CPU_LOOP 500
204
205#define MAX_WAIT_CONUT 1000
206
207#endif /* __PMU_H__ */