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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +00002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#ifndef __ARM_DEF_H__
31#define __ARM_DEF_H__
32
Soby Mathewfec4eb72015-07-01 16:16:20 +010033#include <arch.h>
Dan Handley9df48042015-03-19 18:58:55 +000034#include <common_def.h>
35#include <platform_def.h>
Juan Castillo9b265a82015-05-07 14:52:44 +010036#include <tbbr_img_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000037#include <xlat_tables.h>
38
39
40/******************************************************************************
41 * Definitions common to all ARM standard platforms
42 *****************************************************************************/
43
Juan Castillo7d199412015-12-14 09:35:25 +000044/* Special value used to verify platform parameters from BL2 to BL31 */
Dan Handley9df48042015-03-19 18:58:55 +000045#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
46
Soby Mathewa869de12015-05-08 10:18:59 +010047#define ARM_SYSTEM_COUNT 1
Dan Handley9df48042015-03-19 18:58:55 +000048
49#define ARM_CACHE_WRITEBACK_SHIFT 6
50
Soby Mathewfec4eb72015-07-01 16:16:20 +010051/*
52 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
53 * power levels have a 1:1 mapping with the MPIDR affinity levels.
54 */
55#define ARM_PWR_LVL0 MPIDR_AFFLVL0
56#define ARM_PWR_LVL1 MPIDR_AFFLVL1
Soby Mathewa869de12015-05-08 10:18:59 +010057#define ARM_PWR_LVL2 MPIDR_AFFLVL2
Soby Mathewfec4eb72015-07-01 16:16:20 +010058
59/*
60 * Macros for local power states in ARM platforms encoded by State-ID field
61 * within the power-state parameter.
62 */
63/* Local power state for power domains in Run state. */
64#define ARM_LOCAL_STATE_RUN 0
65/* Local power state for retention. Valid only for CPU power domains */
66#define ARM_LOCAL_STATE_RET 1
67/* Local power state for OFF/power-down. Valid for CPU and cluster power
68 domains */
69#define ARM_LOCAL_STATE_OFF 2
70
Dan Handley9df48042015-03-19 18:58:55 +000071/* Memory location options for TSP */
72#define ARM_TRUSTED_SRAM_ID 0
73#define ARM_TRUSTED_DRAM_ID 1
74#define ARM_DRAM_ID 2
75
76/* The first 4KB of Trusted SRAM are used as shared memory */
77#define ARM_TRUSTED_SRAM_BASE 0x04000000
78#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
79#define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
80
81/* The remaining Trusted SRAM is used to load the BL images */
82#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
83 ARM_SHARED_RAM_SIZE)
84#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
85 ARM_SHARED_RAM_SIZE)
86
87/*
88 * The top 16MB of DRAM1 is configured as secure access only using the TZC
89 * - SCP TZC DRAM: If present, DRAM reserved for SCP use
90 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
91 */
92#define ARM_TZC_DRAM1_SIZE MAKE_ULL(0x01000000)
93
94#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
95 ARM_DRAM1_SIZE - \
96 ARM_SCP_TZC_DRAM1_SIZE)
97#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
98#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
99 ARM_SCP_TZC_DRAM1_SIZE - 1)
100
101#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
102 ARM_DRAM1_SIZE - \
103 ARM_TZC_DRAM1_SIZE)
104#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
105 ARM_SCP_TZC_DRAM1_SIZE)
106#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
107 ARM_AP_TZC_DRAM1_SIZE - 1)
108
109
110#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
111#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
112 ARM_TZC_DRAM1_SIZE)
113#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
114 ARM_NS_DRAM1_SIZE - 1)
115
116#define ARM_DRAM1_BASE MAKE_ULL(0x80000000)
117#define ARM_DRAM1_SIZE MAKE_ULL(0x80000000)
118#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
119 ARM_DRAM1_SIZE - 1)
120
121#define ARM_DRAM2_BASE MAKE_ULL(0x880000000)
122#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
123#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
124 ARM_DRAM2_SIZE - 1)
125
126#define ARM_IRQ_SEC_PHY_TIMER 29
127
128#define ARM_IRQ_SEC_SGI_0 8
129#define ARM_IRQ_SEC_SGI_1 9
130#define ARM_IRQ_SEC_SGI_2 10
131#define ARM_IRQ_SEC_SGI_3 11
132#define ARM_IRQ_SEC_SGI_4 12
133#define ARM_IRQ_SEC_SGI_5 13
134#define ARM_IRQ_SEC_SGI_6 14
135#define ARM_IRQ_SEC_SGI_7 15
136
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000137/*
138 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
139 * terminology. On a GICv2 system or mode, the lists will be merged and treated
140 * as Group 0 interrupts.
141 */
142#define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \
143 ARM_IRQ_SEC_SGI_1, \
144 ARM_IRQ_SEC_SGI_2, \
145 ARM_IRQ_SEC_SGI_3, \
146 ARM_IRQ_SEC_SGI_4, \
147 ARM_IRQ_SEC_SGI_5, \
148 ARM_IRQ_SEC_SGI_7
149
150#define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \
151 ARM_IRQ_SEC_SGI_6
152
Dan Handley9df48042015-03-19 18:58:55 +0000153#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
154 ARM_SHARED_RAM_BASE, \
155 ARM_SHARED_RAM_SIZE, \
Juan Castillo2e86cb12016-01-13 15:01:09 +0000156 MT_DEVICE | MT_RW | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +0000157
158#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
159 ARM_NS_DRAM1_BASE, \
160 ARM_NS_DRAM1_SIZE, \
161 MT_MEMORY | MT_RW | MT_NS)
162
163#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
164 TSP_SEC_MEM_BASE, \
165 TSP_SEC_MEM_SIZE, \
166 MT_MEMORY | MT_RW | MT_SECURE)
167
168
169/*
170 * The number of regions like RO(code), coherent and data required by
171 * different BL stages which need to be mapped in the MMU.
172 */
173#if USE_COHERENT_MEM
174#define ARM_BL_REGIONS 3
175#else
176#define ARM_BL_REGIONS 2
177#endif
178
179#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
180 ARM_BL_REGIONS)
181
182/* Memory mapped Generic timer interfaces */
183#define ARM_SYS_CNTCTL_BASE 0x2a430000
184#define ARM_SYS_CNTREAD_BASE 0x2a800000
185#define ARM_SYS_TIMCTL_BASE 0x2a810000
186
187#define ARM_CONSOLE_BAUDRATE 115200
188
Juan Castillob6132f12015-10-06 14:01:35 +0100189/* Trusted Watchdog constants */
190#define ARM_SP805_TWDG_BASE 0x2a490000
191#define ARM_SP805_TWDG_CLK_HZ 32768
192/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
193 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
194#define ARM_TWDG_TIMEOUT_SEC 128
195#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
196 ARM_TWDG_TIMEOUT_SEC)
197
Dan Handley9df48042015-03-19 18:58:55 +0000198/******************************************************************************
199 * Required platform porting definitions common to all ARM standard platforms
200 *****************************************************************************/
201
202#define ADDR_SPACE_SIZE (1ull << 32)
203
Soby Mathewfec4eb72015-07-01 16:16:20 +0100204/*
205 * This macro defines the deepest retention state possible. A higher state
206 * id will represent an invalid or a power down state.
207 */
208#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
209
210/*
211 * This macro defines the deepest power down states possible. Any state ID
212 * higher than this is invalid.
213 */
214#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
215
Dan Handley9df48042015-03-19 18:58:55 +0000216/*
217 * Some data must be aligned on the biggest cache line size in the platform.
218 * This is known only to the platform as it might have a combination of
219 * integrated and external caches.
220 */
221#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
222
Dan Handley9df48042015-03-19 18:58:55 +0000223
224/*******************************************************************************
225 * BL1 specific defines.
226 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
227 * addresses.
228 ******************************************************************************/
229#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
230#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
231 + PLAT_ARM_TRUSTED_ROM_SIZE)
232/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000233 * Put BL1 RW at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000234 */
Dan Handley9df48042015-03-19 18:58:55 +0000235#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
236 ARM_BL_RAM_SIZE - \
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000237 PLAT_ARM_MAX_BL1_RW_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000238#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
239
240/*******************************************************************************
241 * BL2 specific defines.
242 ******************************************************************************/
243/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000244 * Put BL2 just below BL31.
Dan Handley9df48042015-03-19 18:58:55 +0000245 */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000246#define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000247#define BL2_LIMIT BL31_BASE
248
249/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000250 * BL31 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000251 ******************************************************************************/
252/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000253 * Put BL31 at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000254 */
255#define BL31_BASE (ARM_BL_RAM_BASE + \
256 ARM_BL_RAM_SIZE - \
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000257 PLAT_ARM_MAX_BL31_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000258#define BL31_PROGBITS_LIMIT BL1_RW_BASE
259#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
260
261/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000262 * BL32 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000263 ******************************************************************************/
264/*
265 * On ARM standard platforms, the TSP can execute from Trusted SRAM,
266 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
267 * controller.
268 */
269#if ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
270# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
271# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
272# define TSP_PROGBITS_LIMIT BL2_BASE
273# define BL32_BASE ARM_BL_RAM_BASE
274# define BL32_LIMIT BL31_BASE
275#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
276# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
277# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
278# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
279# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
280 + (1 << 21))
281#elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
282# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
283# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
284# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
285# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
286 ARM_AP_TZC_DRAM1_SIZE)
287#else
288# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
289#endif
290
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100291/*******************************************************************************
292 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
293 ******************************************************************************/
294#define BL2U_BASE BL2_BASE
295#define BL2U_LIMIT BL31_BASE
296#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
297#define NS_BL1U_BASE (V2M_FLASH0_BASE + 0x03EB8000)
298
Dan Handley9df48042015-03-19 18:58:55 +0000299/*
300 * ID of the secure physical generic timer interrupt used by the TSP.
301 */
302#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
303
304
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100305/*
306 * One cache line needed for bakery locks on ARM platforms
307 */
308#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
309
310
Dan Handley9df48042015-03-19 18:58:55 +0000311#endif /* __ARM_DEF_H__ */