Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 1 | /* |
Varun Wadekar | b556828 | 2016-12-13 18:04:35 -0800 | [diff] [blame] | 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Varun Wadekar | b556828 | 2016-12-13 18:04:35 -0800 | [diff] [blame] | 31 | #ifndef __MCE_PRIVATE_H__ |
| 32 | #define __MCE_PRIVATE_H__ |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 33 | |
| 34 | #include <mmio.h> |
| 35 | #include <tegra_def.h> |
| 36 | |
| 37 | /******************************************************************************* |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 38 | * Macros to prepare CSTATE info request |
| 39 | ******************************************************************************/ |
| 40 | /* Description of the parameters for UPDATE_CSTATE_INFO request */ |
| 41 | #define CLUSTER_CSTATE_MASK 0x7 |
| 42 | #define CLUSTER_CSTATE_SHIFT 0 |
| 43 | #define CLUSTER_CSTATE_UPDATE_BIT (1 << 7) |
| 44 | #define CCPLEX_CSTATE_MASK 0x3 |
| 45 | #define CCPLEX_CSTATE_SHIFT 8 |
| 46 | #define CCPLEX_CSTATE_UPDATE_BIT (1 << 15) |
| 47 | #define SYSTEM_CSTATE_MASK 0xF |
| 48 | #define SYSTEM_CSTATE_SHIFT 16 |
| 49 | #define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22 |
| 50 | #define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1 << 22) |
| 51 | #define SYSTEM_CSTATE_UPDATE_BIT (1 << 23) |
| 52 | #define CSTATE_WAKE_MASK_UPDATE_BIT (1 << 31) |
| 53 | #define CSTATE_WAKE_MASK_SHIFT 32 |
| 54 | #define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFF |
| 55 | |
| 56 | /******************************************************************************* |
| 57 | * Auto-CC3 control macros |
| 58 | ******************************************************************************/ |
| 59 | #define MCE_AUTO_CC3_FREQ_MASK 0x1FF |
| 60 | #define MCE_AUTO_CC3_FREQ_SHIFT 0 |
| 61 | #define MCE_AUTO_CC3_VTG_MASK 0x7F |
| 62 | #define MCE_AUTO_CC3_VTG_SHIFT 16 |
| 63 | #define MCE_AUTO_CC3_ENABLE_BIT (1 << 31) |
| 64 | |
| 65 | /******************************************************************************* |
| 66 | * Macros for the 'IS_SC7_ALLOWED' command |
| 67 | ******************************************************************************/ |
| 68 | #define MCE_SC7_ALLOWED_MASK 0x7 |
| 69 | #define MCE_SC7_WAKE_TIME_SHIFT 32 |
| 70 | |
| 71 | /******************************************************************************* |
| 72 | * Macros for 'read/write ctats' commands |
| 73 | ******************************************************************************/ |
| 74 | #define MCE_CSTATE_STATS_TYPE_SHIFT 32 |
| 75 | #define MCE_CSTATE_WRITE_DATA_LO_MASK 0xF |
| 76 | |
| 77 | /******************************************************************************* |
| 78 | * Macros for 'update crossover threshold' command |
| 79 | ******************************************************************************/ |
| 80 | #define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32 |
| 81 | |
| 82 | /******************************************************************************* |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 83 | * MCA command struct |
| 84 | ******************************************************************************/ |
| 85 | typedef union mca_cmd { |
| 86 | struct command { |
| 87 | uint8_t cmd; |
| 88 | uint8_t idx; |
| 89 | uint8_t subidx; |
| 90 | } command; |
| 91 | struct input { |
| 92 | uint32_t low; |
| 93 | uint32_t high; |
| 94 | } input; |
| 95 | uint64_t data; |
| 96 | } mca_cmd_t; |
| 97 | |
| 98 | /******************************************************************************* |
| 99 | * MCA argument struct |
| 100 | ******************************************************************************/ |
| 101 | typedef union mca_arg { |
| 102 | struct err { |
Stephen Warren | e370ad9 | 2017-02-28 17:12:35 -0700 | [diff] [blame^] | 103 | uint32_t error:8; |
| 104 | uint32_t unused:24; |
| 105 | uint32_t unused2:24; |
| 106 | uint32_t finish:8; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 107 | } err; |
| 108 | struct arg { |
| 109 | uint32_t low; |
| 110 | uint32_t high; |
| 111 | } arg; |
| 112 | uint64_t data; |
| 113 | } mca_arg_t; |
| 114 | |
| 115 | /******************************************************************************* |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 116 | * Uncore PERFMON ARI struct |
| 117 | ******************************************************************************/ |
| 118 | typedef union uncore_perfmon_req { |
| 119 | struct perfmon_command { |
| 120 | /* |
| 121 | * Commands: 0 = READ, 1 = WRITE |
| 122 | */ |
Stephen Warren | e370ad9 | 2017-02-28 17:12:35 -0700 | [diff] [blame^] | 123 | uint32_t cmd:8; |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 124 | /* |
| 125 | * The unit group: L2=0, L3=1, ROC=2, MC=3, IOB=4 |
| 126 | */ |
Stephen Warren | e370ad9 | 2017-02-28 17:12:35 -0700 | [diff] [blame^] | 127 | uint32_t grp:4; |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 128 | /* |
| 129 | * Unit selector: Selects the unit instance, with 0 = Unit |
| 130 | * = (number of units in group) - 1. |
| 131 | */ |
Stephen Warren | e370ad9 | 2017-02-28 17:12:35 -0700 | [diff] [blame^] | 132 | uint32_t unit:4; |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 133 | /* |
| 134 | * Selects the uncore perfmon register to access |
| 135 | */ |
Stephen Warren | e370ad9 | 2017-02-28 17:12:35 -0700 | [diff] [blame^] | 136 | uint32_t reg:8; |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 137 | /* |
| 138 | * Counter number. Selects which counter to use for |
| 139 | * registers NV_PMEVCNTR and NV_PMEVTYPER. |
| 140 | */ |
Stephen Warren | e370ad9 | 2017-02-28 17:12:35 -0700 | [diff] [blame^] | 141 | uint32_t counter:8; |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 142 | } perfmon_command; |
| 143 | struct perfmon_status { |
| 144 | /* |
| 145 | * Resulting command status |
| 146 | */ |
Stephen Warren | e370ad9 | 2017-02-28 17:12:35 -0700 | [diff] [blame^] | 147 | uint32_t val:8; |
| 148 | uint32_t unused:24; |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 149 | } perfmon_status; |
| 150 | uint64_t data; |
| 151 | } uncore_perfmon_req_t; |
| 152 | |
| 153 | #define UNCORE_PERFMON_CMD_READ 0 |
| 154 | #define UNCORE_PERFMON_CMD_WRITE 1 |
| 155 | |
| 156 | #define UNCORE_PERFMON_CMD_MASK 0xFF |
| 157 | #define UNCORE_PERFMON_UNIT_GRP_MASK 0xF |
| 158 | #define UNCORE_PERFMON_SELECTOR_MASK 0xF |
| 159 | #define UNCORE_PERFMON_REG_MASK 0xFF |
| 160 | #define UNCORE_PERFMON_CTR_MASK 0xFF |
| 161 | #define UNCORE_PERFMON_RESP_STATUS_MASK 0xFF |
| 162 | |
| 163 | /******************************************************************************* |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 164 | * Structure populated by arch specific code to export routines which perform |
| 165 | * common low level MCE functions |
| 166 | ******************************************************************************/ |
| 167 | typedef struct arch_mce_ops { |
| 168 | /* |
| 169 | * This ARI request sets up the MCE to start execution on assertion |
| 170 | * of STANDBYWFI, update the core power state and expected wake time, |
| 171 | * then determine the proper power state to enter. |
| 172 | */ |
| 173 | int (*enter_cstate)(uint32_t ari_base, uint32_t state, |
| 174 | uint32_t wake_time); |
| 175 | /* |
| 176 | * This ARI request allows updating of the CLUSTER_CSTATE, |
| 177 | * CCPLEX_CSTATE, and SYSTEM_CSTATE register values. |
| 178 | */ |
| 179 | int (*update_cstate_info)(uint32_t ari_base, |
| 180 | uint32_t cluster, |
| 181 | uint32_t ccplex, |
| 182 | uint32_t system, |
| 183 | uint8_t sys_state_force, |
| 184 | uint32_t wake_mask, |
| 185 | uint8_t update_wake_mask); |
| 186 | /* |
| 187 | * This ARI request allows updating of power state crossover |
| 188 | * threshold times. An index value specifies which crossover |
| 189 | * state is being updated. |
| 190 | */ |
| 191 | int (*update_crossover_time)(uint32_t ari_base, |
| 192 | uint32_t type, |
| 193 | uint32_t time); |
| 194 | /* |
| 195 | * This ARI request allows read access to statistical information |
| 196 | * related to power states. |
| 197 | */ |
| 198 | uint64_t (*read_cstate_stats)(uint32_t ari_base, |
| 199 | uint32_t state); |
| 200 | /* |
| 201 | * This ARI request allows write access to statistical information |
| 202 | * related to power states. |
| 203 | */ |
| 204 | int (*write_cstate_stats)(uint32_t ari_base, |
| 205 | uint32_t state, |
| 206 | uint32_t stats); |
| 207 | /* |
| 208 | * This ARI request allows the CPU to understand the features |
| 209 | * supported by the MCE firmware. |
| 210 | */ |
| 211 | uint64_t (*call_enum_misc)(uint32_t ari_base, uint32_t cmd, |
| 212 | uint32_t data); |
| 213 | /* |
| 214 | * This ARI request allows querying the CCPLEX to determine if |
| 215 | * the CCx state is allowed given a target core C-state and wake |
| 216 | * time. If the CCx state is allowed, the response indicates CCx |
| 217 | * must be entered. If the CCx state is not allowed, the response |
| 218 | * indicates CC6/CC7 can't be entered |
| 219 | */ |
| 220 | int (*is_ccx_allowed)(uint32_t ari_base, uint32_t state, |
| 221 | uint32_t wake_time); |
| 222 | /* |
| 223 | * This ARI request allows querying the CCPLEX to determine if |
| 224 | * the SC7 state is allowed given a target core C-state and wake |
| 225 | * time. If the SC7 state is allowed, all cores but the associated |
| 226 | * core are offlined (WAKE_EVENTS are set to 0) and the response |
| 227 | * indicates SC7 must be entered. If the SC7 state is not allowed, |
| 228 | * the response indicates SC7 can't be entered |
| 229 | */ |
| 230 | int (*is_sc7_allowed)(uint32_t ari_base, uint32_t state, |
| 231 | uint32_t wake_time); |
| 232 | /* |
| 233 | * This ARI request allows a core to bring another offlined core |
| 234 | * back online to the C0 state. Note that a core is offlined by |
| 235 | * entering a C-state where the WAKE_MASK is all 0. |
| 236 | */ |
| 237 | int (*online_core)(uint32_t ari_base, uint32_t cpuid); |
| 238 | /* |
| 239 | * This ARI request allows the CPU to enable/disable Auto-CC3 idle |
| 240 | * state. |
| 241 | */ |
| 242 | int (*cc3_ctrl)(uint32_t ari_base, |
| 243 | uint32_t freq, |
| 244 | uint32_t volt, |
| 245 | uint8_t enable); |
| 246 | /* |
| 247 | * This ARI request allows updating the reset vector register for |
| 248 | * D15 and A57 CPUs. |
| 249 | */ |
Krishna Sitaraman | d007f76 | 2016-09-02 16:53:04 -0700 | [diff] [blame] | 250 | int (*update_reset_vector)(uint32_t ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 251 | /* |
| 252 | * This ARI request instructs the ROC to flush A57 data caches in |
| 253 | * order to maintain coherency with the Denver cluster. |
| 254 | */ |
| 255 | int (*roc_flush_cache)(uint32_t ari_base); |
| 256 | /* |
| 257 | * This ARI request instructs the ROC to flush A57 data caches along |
| 258 | * with the caches covering ARM code in order to maintain coherency |
| 259 | * with the Denver cluster. |
| 260 | */ |
| 261 | int (*roc_flush_cache_trbits)(uint32_t ari_base); |
| 262 | /* |
| 263 | * This ARI request instructs the ROC to clean A57 data caches along |
| 264 | * with the caches covering ARM code in order to maintain coherency |
| 265 | * with the Denver cluster. |
| 266 | */ |
| 267 | int (*roc_clean_cache)(uint32_t ari_base); |
| 268 | /* |
| 269 | * This ARI request reads/writes the Machine Check Arch. (MCA) |
| 270 | * registers. |
| 271 | */ |
| 272 | uint64_t (*read_write_mca)(uint32_t ari_base, |
| 273 | mca_cmd_t cmd, |
| 274 | uint64_t *data); |
| 275 | /* |
| 276 | * Some MC GSC (General Security Carveout) register values are |
| 277 | * expected to be changed by TrustZone secure ARM code after boot. |
| 278 | * Since there is no hardware mechanism for the CCPLEX to know |
| 279 | * that an MC GSC register has changed to allow it to update its |
| 280 | * own internal GSC register, there needs to be a mechanism that |
| 281 | * can be used by ARM code to cause the CCPLEX to update its GSC |
| 282 | * register value. This ARI request allows updating the GSC register |
| 283 | * value for a certain carveout in the CCPLEX. |
| 284 | */ |
| 285 | int (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx); |
| 286 | /* |
| 287 | * This ARI request instructs the CCPLEX to either shutdown or |
| 288 | * reset the entire system |
| 289 | */ |
| 290 | void (*enter_ccplex_state)(uint32_t ari_base, uint32_t state_idx); |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 291 | /* |
| 292 | * This ARI request reads/writes data from/to Uncore PERFMON |
| 293 | * registers |
| 294 | */ |
| 295 | int (*read_write_uncore_perfmon)(uint32_t ari_base, |
| 296 | uncore_perfmon_req_t req, uint64_t *data); |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 297 | /* |
| 298 | * This ARI implements ARI_MISC_CCPLEX commands. This can be |
| 299 | * used to enable/disable coresight clock gating. |
| 300 | */ |
| 301 | void (*misc_ccplex)(uint32_t ari_base, uint32_t index, |
| 302 | uint32_t value); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 303 | } arch_mce_ops_t; |
| 304 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 305 | /* declarations for ARI/NVG handler functions */ |
| 306 | int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 307 | int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, |
| 308 | uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, |
| 309 | uint8_t update_wake_mask); |
| 310 | int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); |
| 311 | uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state); |
| 312 | int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); |
| 313 | uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data); |
| 314 | int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 315 | int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 316 | int ari_online_core(uint32_t ari_base, uint32_t core); |
| 317 | int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); |
Krishna Sitaraman | d007f76 | 2016-09-02 16:53:04 -0700 | [diff] [blame] | 318 | int ari_reset_vector_update(uint32_t ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 319 | int ari_roc_flush_cache_trbits(uint32_t ari_base); |
| 320 | int ari_roc_flush_cache(uint32_t ari_base); |
| 321 | int ari_roc_clean_cache(uint32_t ari_base); |
| 322 | uint64_t ari_read_write_mca(uint32_t ari_base, mca_cmd_t cmd, uint64_t *data); |
| 323 | int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx); |
| 324 | void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx); |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 325 | int ari_read_write_uncore_perfmon(uint32_t ari_base, |
| 326 | uncore_perfmon_req_t req, uint64_t *data); |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 327 | void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 328 | |
| 329 | int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 330 | int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, |
| 331 | uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, |
| 332 | uint8_t update_wake_mask); |
| 333 | int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); |
| 334 | uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state); |
| 335 | int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t val); |
| 336 | int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 337 | int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); |
| 338 | int nvg_online_core(uint32_t ari_base, uint32_t core); |
| 339 | int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); |
| 340 | |
Varun Wadekar | b556828 | 2016-12-13 18:04:35 -0800 | [diff] [blame] | 341 | #endif /* __MCE_PRIVATE_H__ */ |