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developer550bf5e2016-07-11 16:05:23 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
developer550bf5e2016-07-11 16:05:23 +08005 */
6
Isla Mitchelle3631462017-07-14 10:46:32 +01007
developer550bf5e2016-07-11 16:05:23 +08008#include <arch_helpers.h>
Isla Mitchelle3631462017-07-14 10:46:32 +01009#include <debug.h>
developer550bf5e2016-07-11 16:05:23 +080010#include <mmio.h>
11#include <mt_cpuxgpt.h>
developer550bf5e2016-07-11 16:05:23 +080012#include <platform.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010013#include <stdint.h>
developer550bf5e2016-07-11 16:05:23 +080014#define CPUXGPT_BASE 0x10200000
15#define INDEX_BASE (CPUXGPT_BASE+0x0674)
16#define CTL_BASE (CPUXGPT_BASE+0x0670)
17
18uint64_t normal_time_base;
19uint64_t atf_time_base;
20
21void sched_clock_init(uint64_t normal_base, uint64_t atf_base)
22{
23 normal_time_base = normal_base;
24 atf_time_base = atf_base;
25}
26
27uint64_t sched_clock(void)
28{
29 uint64_t cval;
30
31 cval = (((read_cntpct_el0() - atf_time_base)*1000)/
32 SYS_COUNTER_FREQ_IN_MHZ) + normal_time_base;
33 return cval;
34}
35
36/*
37 * Return: 0 - Trying to disable the CPUXGPT control bit,
38 * and not allowed to disable it.
39 * Return: 1 - reg_addr is not realted to disable the control bit.
40 */
41unsigned char check_cpuxgpt_write_permission(unsigned int reg_addr,
42 unsigned int reg_value)
43{
44 unsigned int idx;
45 unsigned int ctl_val;
46
47 if (reg_addr == CTL_BASE) {
48 idx = mmio_read_32(INDEX_BASE);
49
50 /* idx 0: CPUXGPT system control */
51 if (idx == 0) {
52 ctl_val = mmio_read_32(CTL_BASE);
53 if (ctl_val & 1) {
54 /*
55 * if enable bit already set,
56 * then bit 0 is not allow to set as 0
57 */
58 if (!(reg_value & 1))
59 return 0;
60 }
61 }
62 }
63 return 1;
64}
65