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Haojian Zhuang602362d2017-06-01 12:15:14 +08001#
2# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Victor Chong2d9a42d2017-08-17 15:21:10 +09007# Enable version2 of image loading
8LOAD_IMAGE_V2 := 1
9
Victor Chong91287682017-05-28 00:14:37 +090010# On Hikey960, the TSP can execute from TZC secure area in DRAM.
11HIKEY960_TSP_RAM_LOCATION := dram
12ifeq (${HIKEY960_TSP_RAM_LOCATION}, dram)
13 HIKEY960_TSP_RAM_LOCATION_ID = HIKEY960_DRAM_ID
14else ifeq (${HIKEY960_TSP_RAM_LOCATION}, sram)
15 HIKEY960_TSP_RAM_LOCATION_ID := HIKEY960_SRAM_ID
16else
17 $(error "Currently unsupported HIKEY960_TSP_RAM_LOCATION value")
18endif
19
Haojian Zhuang602362d2017-06-01 12:15:14 +080020CRASH_CONSOLE_BASE := PL011_UART6_BASE
21COLD_BOOT_SINGLE_CPU := 1
22PROGRAMMABLE_RESET_ADDRESS := 1
23
24# Process flags
Victor Chong91287682017-05-28 00:14:37 +090025$(eval $(call add_define,HIKEY960_TSP_RAM_LOCATION_ID))
Haojian Zhuang602362d2017-06-01 12:15:14 +080026$(eval $(call add_define,CRASH_CONSOLE_BASE))
27
Victor Chong7d787f52017-08-16 13:53:56 +090028# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
29# in the FIP if the platform requires.
30ifneq ($(BL32_EXTRA1),)
31$(eval $(call FIP_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
32endif
33ifneq ($(BL32_EXTRA2),)
34$(eval $(call FIP_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
35endif
36
Haojian Zhuang602362d2017-06-01 12:15:14 +080037ENABLE_PLAT_COMPAT := 0
38
39USE_COHERENT_MEM := 1
40
41PLAT_INCLUDES := -Iinclude/common/tbbr \
42 -Iplat/hisilicon/hikey960/include
43
44PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
45 drivers/delay_timer/delay_timer.c \
46 drivers/delay_timer/generic_delay_timer.c \
47 lib/aarch64/xlat_tables.c \
48 plat/hisilicon/hikey960/aarch64/hikey960_common.c \
49 plat/hisilicon/hikey960/hikey960_boardid.c
50
51HIKEY960_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
52 drivers/arm/gic/v2/gicv2_main.c \
53 drivers/arm/gic/v2/gicv2_helpers.c \
54 plat/common/plat_gicv2.c
55
56BL1_SOURCES += bl1/tbbr/tbbr_img_desc.c \
57 drivers/io/io_block.c \
58 drivers/io/io_fip.c \
59 drivers/io/io_storage.c \
60 drivers/synopsys/ufs/dw_ufs.c \
61 drivers/ufs/ufs.c \
62 lib/cpus/aarch64/cortex_a53.S \
63 plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
64 plat/hisilicon/hikey960/hikey960_bl1_setup.c \
65 plat/hisilicon/hikey960/hikey960_io_storage.c \
66 ${HIKEY960_GIC_SOURCES}
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080067
68BL2_SOURCES += drivers/io/io_block.c \
69 drivers/io/io_fip.c \
70 drivers/io/io_storage.c \
71 drivers/ufs/ufs.c \
72 plat/hisilicon/hikey960/hikey960_bl2_setup.c \
73 plat/hisilicon/hikey960/hikey960_io_storage.c \
74 plat/hisilicon/hikey960/hikey960_mcu_load.c
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080075
Victor Chong2d9a42d2017-08-17 15:21:10 +090076ifeq (${LOAD_IMAGE_V2},1)
77BL2_SOURCES += plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c \
78 plat/hisilicon/hikey960/hikey960_image_load.c \
79 common/desc_image_load.c
Victor Chong7d787f52017-08-16 13:53:56 +090080
81ifeq (${SPD},opteed)
82BL2_SOURCES += lib/optee/optee_utils.c
83endif
Victor Chong2d9a42d2017-08-17 15:21:10 +090084endif
85
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080086BL31_SOURCES += drivers/arm/cci/cci.c \
87 lib/cpus/aarch64/cortex_a53.S \
88 lib/cpus/aarch64/cortex_a72.S \
89 lib/cpus/aarch64/cortex_a73.S \
90 plat/common/aarch64/plat_psci_common.c \
91 plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
92 plat/hisilicon/hikey960/hikey960_bl31_setup.c \
93 plat/hisilicon/hikey960/hikey960_pm.c \
94 plat/hisilicon/hikey960/hikey960_topology.c \
95 plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c \
96 plat/hisilicon/hikey960/drivers/ipc/hisi_ipc.c \
97 ${HIKEY960_GIC_SOURCES}
Victor Chongcb27a352017-07-12 01:07:29 +090098
99# Enable workarounds for selected Cortex-A53 errata.
100ERRATA_A53_836870 := 1
101ERRATA_A53_843419 := 1
102ERRATA_A53_855873 := 1