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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <assert.h>
32#include <bl_common.h>
33#include <bl31.h>
34#include <console.h>
35#include <debug.h>
36#include <errno.h>
37#include <plat_arm.h>
38#include <platform.h>
39#include "zynqmp_private.h"
40
Soren Brinkmann6d1ba582016-07-08 14:45:14 -070041#define BL31_END (unsigned long)(&__BL31_END__)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080042
43/*
44 * The next 2 constants identify the extents of the coherent memory region.
45 * These addresses are used by the MMU setup code and therefore they must be
46 * page-aligned. It is the responsibility of the linker script to ensure that
47 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
48 * refer to page-aligned addresses.
49 */
50#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
51#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
52
53static entry_point_info_t bl32_image_ep_info;
54static entry_point_info_t bl33_image_ep_info;
55
56/*
57 * Return a pointer to the 'entry_point_info' structure of the next image for
58 * the security state specified. BL33 corresponds to the non-secure image type
59 * while BL32 corresponds to the secure image type. A NULL pointer is returned
60 * if the image does not exist.
61 */
62entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
63{
64 assert(sec_state_is_valid(type));
65
66 if (type == NON_SECURE)
67 return &bl33_image_ep_info;
68
69 return &bl32_image_ep_info;
70}
71
72/*
73 * Perform any BL31 specific platform actions. Here is an opportunity to copy
74 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
75 * are lost (potentially). This needs to be done before the MMU is initialized
76 * so that the memory layout can be used while creating page tables.
77 */
78void bl31_early_platform_setup(bl31_params_t *from_bl2,
79 void *plat_params_from_bl2)
80{
81 /* Initialize the console to provide early debug support */
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -070082 console_init(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(),
Soren Brinkmann76fcae32016-03-06 20:16:27 -080083 ZYNQMP_UART_BAUDRATE);
84
85 /* Initialize the platform config for future decision making */
86 zynqmp_config_setup();
87
88 /* There are no parameters from BL2 if BL31 is a reset vector */
89 assert(from_bl2 == NULL);
90 assert(plat_params_from_bl2 == NULL);
91
92 /*
93 * Do initial security configuration to allow DRAM/device access. On
94 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but
95 * other platforms might have more programmable security devices
96 * present.
97 */
98
Michal Simekef8f5592015-06-15 14:22:50 +020099 /* Populate common information for BL32 and BL33 */
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800100 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
101 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800102 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800103 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
104
Michal Simekef8f5592015-06-15 14:22:50 +0200105 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
106 /* use build time defaults in JTAG boot mode */
107 bl32_image_ep_info.pc = BL32_BASE;
108 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
109 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
110 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
111 DISABLE_ALL_EXCEPTIONS);
112 } else {
113 /* use parameters from FSBL */
114 fsbl_atf_handover(&bl32_image_ep_info, &bl33_image_ep_info);
115 }
116
117 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800118 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
119}
120
121void bl31_platform_setup(void)
122{
123 /* Initialize the gic cpu and distributor interfaces */
124 plat_arm_gic_driver_init();
125 plat_arm_gic_init();
126}
127
128void bl31_plat_runtime_setup(void)
129{
130}
131
132/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100133 * Perform the very early platform specific architectural setup here.
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800134 */
135void bl31_plat_arch_setup(void)
136{
137 plat_arm_interconnect_init();
138 plat_arm_interconnect_enter_coherency();
139
Soren Brinkmann6d1ba582016-07-08 14:45:14 -0700140 arm_setup_page_tables(BL31_BASE,
141 BL31_END - BL31_BASE,
142 BL_CODE_BASE,
143 BL_CODE_LIMIT,
144 BL_RO_DATA_BASE,
145 BL_RO_DATA_LIMIT,
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800146 BL31_COHERENT_RAM_BASE,
147 BL31_COHERENT_RAM_LIMIT);
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100148 enable_mmu_el3(0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800149}