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Dan Handley9df48042015-03-19 18:58:55 +00001/*
2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arm_def.h>
32#include <debug.h>
33#include <platform_def.h>
34#include <tzc400.h>
35
36
37/* Weak definitions may be overridden in specific ARM standard platform */
38#pragma weak plat_arm_security_setup
39
40
41/*******************************************************************************
42 * Initialize the TrustZone Controller for ARM standard platforms.
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000043 * Configure:
44 * - Region 0 with no access;
45 * - Region 1 with secure access only;
46 * - the remaining DRAM regions access from the given Non-Secure masters.
47 *
48 * When booting an EL3 payload, this is simplified: we configure region 0 with
49 * secure access only and do not enable any other region.
Dan Handley9df48042015-03-19 18:58:55 +000050 ******************************************************************************/
Soby Mathew9c708b52016-02-26 14:23:19 +000051void arm_tzc400_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +000052{
53 INFO("Configuring TrustZone Controller\n");
54
Soby Mathew9c708b52016-02-26 14:23:19 +000055 tzc400_init(PLAT_ARM_TZC_BASE);
Dan Handley9df48042015-03-19 18:58:55 +000056
57 /* Disable filters. */
Soby Mathew9c708b52016-02-26 14:23:19 +000058 tzc400_disable_filters();
Dan Handley9df48042015-03-19 18:58:55 +000059
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000060#ifndef EL3_PAYLOAD_BASE
Dan Handley9df48042015-03-19 18:58:55 +000061 /* Region 0 set to no access by default */
Soby Mathew9c708b52016-02-26 14:23:19 +000062 tzc400_configure_region0(TZC_REGION_S_NONE, 0);
Dan Handley9df48042015-03-19 18:58:55 +000063
64 /* Region 1 set to cover Secure part of DRAM */
Soby Mathew9c708b52016-02-26 14:23:19 +000065 tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 1,
Dan Handley9df48042015-03-19 18:58:55 +000066 ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END,
67 TZC_REGION_S_RDWR,
68 0);
69
70 /* Region 2 set to cover Non-Secure access to 1st DRAM address range.
71 * Apply the same configuration to given filters in the TZC. */
Soby Mathew9c708b52016-02-26 14:23:19 +000072 tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 2,
Dan Handley9df48042015-03-19 18:58:55 +000073 ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END,
74 TZC_REGION_S_NONE,
75 PLAT_ARM_TZC_NS_DEV_ACCESS);
76
77 /* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
Soby Mathew9c708b52016-02-26 14:23:19 +000078 tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 3,
Dan Handley9df48042015-03-19 18:58:55 +000079 ARM_DRAM2_BASE, ARM_DRAM2_END,
80 TZC_REGION_S_NONE,
81 PLAT_ARM_TZC_NS_DEV_ACCESS);
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000082#else
83 /* Allow secure access only to DRAM for EL3 payloads. */
Soby Mathew9c708b52016-02-26 14:23:19 +000084 tzc400_configure_region0(TZC_REGION_S_RDWR, 0);
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000085#endif /* EL3_PAYLOAD_BASE */
Dan Handley9df48042015-03-19 18:58:55 +000086
87 /*
88 * Raise an exception if a NS device tries to access secure memory
89 * TODO: Add interrupt handling support.
90 */
Soby Mathew9c708b52016-02-26 14:23:19 +000091 tzc400_set_action(TZC_ACTION_ERR);
Dan Handley9df48042015-03-19 18:58:55 +000092
93 /* Enable filters. */
Soby Mathew9c708b52016-02-26 14:23:19 +000094 tzc400_enable_filters();
Dan Handley9df48042015-03-19 18:58:55 +000095}
96
97void plat_arm_security_setup(void)
98{
Soby Mathew9c708b52016-02-26 14:23:19 +000099 arm_tzc400_setup();
Dan Handley9df48042015-03-19 18:58:55 +0000100}