blob: 62f4059999d0bc3281a5c7d1af7c6c94cdbccfeb [file] [log] [blame]
Nariman Poushin0ece80f2018-02-26 06:52:04 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __PLATFORM_DEF_H__
8#define __PLATFORM_DEF_H__
9
10#include <arm_def.h>
11#include <board_arm_def.h>
12#include <board_css_def.h>
13#include <common_def.h>
14#include <css_def.h>
15#include <soc_css_def.h>
16
17#define CSS_SGI_MAX_CORES_PER_CLUSTER 4
18
19/* CPU topology */
20#define PLAT_ARM_CLUSTER_COUNT 2
21#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
22 CSS_SGI_MAX_CORES_PER_CLUSTER)
23
24#if ARM_BOARD_OPTIMISE_MEM
25
26#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
27# define PLAT_ARM_MMAP_ENTRIES 6
28# define MAX_XLAT_TABLES 4
29#else
30# define PLAT_ARM_MMAP_ENTRIES 10
31# define MAX_XLAT_TABLES 5
32#endif
33
34#if TRUSTED_BOARD_BOOT
35# define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000
36#else
37# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000
38#endif
39
40#if TRUSTED_BOARD_BOOT
41# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
42#else
43# define PLAT_ARM_MAX_BL2_SIZE 0xC000
44#endif
45
46#endif /* ARM_BOARD_OPTIMISE_MEM */
47
48#define PLAT_ARM_NSTIMER_FRAME_ID 0
49
50#define PLAT_CSS_MHU_BASE 0x45000000
51
52#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
53#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */
54
55#define PLAT_MAX_PWR_LVL 1
56
57#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \
58 CSS_IRQ_MHU
59
60#define PLAT_ARM_G0_IRQS ARM_G0_IRQS
61
62#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
63#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
64
65#define CSS_SGI_DEVICE_BASE (0x20000000)
66#define CSS_SGI_DEVICE_SIZE (0x20000000)
67#define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \
68 CSS_SGI_DEVICE_BASE, \
69 CSS_SGI_DEVICE_SIZE, \
70 MT_DEVICE | MT_RW | MT_SECURE)
71
72#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000
73#define SGI_BOOT_CFG_ADDR 0x45410000
74#define PLAT_CSS_PRIMARY_CPU_SHIFT 8
75#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 6
76
77/* GIC related constants */
78#define PLAT_ARM_GICD_BASE 0x30000000
79#define PLAT_ARM_GICC_BASE 0x2C000000
80#define PLAT_ARM_GICR_BASE 0x300C0000
81
82/* Platform ID address */
83#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
84#ifndef __ASSEMBLY__
85/* SSC_VERSION related accessors */
86/* Returns the part number of the platform */
87#define GET_SGI_PART_NUM \
88 GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
89/* Returns the configuration number of the platform */
90#define GET_SGI_CONFIG_NUM \
91 GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
92#endif /* __ASSEMBLY__ */
93
94#endif /* __PLATFORM_DEF_H__ */