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Antonio Nino Diazae6779e2017-11-06 14:49:04 +00001/*
Mario Bălănică40656462023-12-01 05:43:53 +02002 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +01007#include <stdint.h>
Antonio Nino Diazae6779e2017-11-06 14:49:04 +00008
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <platform_def.h>
10
11#include <arch.h>
12
Andre Przywara4ea3bd32019-07-09 14:32:11 +010013#include <rpi_shared.h>
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000014
15/* The power domain tree descriptor */
16static unsigned char power_domain_tree_desc[] = {
17 /* Number of root nodes */
18 PLATFORM_CLUSTER_COUNT,
19 /* Number of children for the first node */
20 PLATFORM_CLUSTER0_CORE_COUNT,
21};
22
23/*******************************************************************************
24 * This function returns the ARM default topology tree information.
25 ******************************************************************************/
26const unsigned char *plat_get_power_domain_tree_desc(void)
27{
28 return power_domain_tree_desc;
29}
30
31/*******************************************************************************
32 * This function implements a part of the critical interface between the psci
33 * generic layer and the platform that allows the former to query the platform
34 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
35 * in case the MPIDR is invalid.
36 ******************************************************************************/
37int plat_core_pos_by_mpidr(u_register_t mpidr)
38{
39 unsigned int cluster_id, cpu_id;
40
41 mpidr &= MPIDR_AFFINITY_MASK;
Mario Bălănică40656462023-12-01 05:43:53 +020042
43 /*
44 * When MT is set, lowest affinity represents the thread ID.
45 * Since we only support one thread per core, discard this field
46 * so cluster and core IDs go back into Aff1 and Aff0 respectively.
47 * The upper bits are also affected, but plat_rpi3_calc_core_pos()
48 * does not use them.
49 */
50 if ((read_mpidr() & MPIDR_MT_MASK) != 0) {
51 if (MPIDR_AFFLVL0_VAL(mpidr) != 0) {
52 return -1;
53 }
54 mpidr >>= MPIDR_AFFINITY_BITS;
55 }
56
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000057 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) {
58 return -1;
59 }
60
Mario Bălănică40656462023-12-01 05:43:53 +020061 cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
62 cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
Antonio Nino Diazae6779e2017-11-06 14:49:04 +000063
64 if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
65 return -1;
66 }
67
68 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
69 return -1;
70 }
71
72 return plat_rpi3_calc_core_pos(mpidr);
73}