Jacky Bai | 4d93d1d | 2020-07-02 14:39:58 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | /** |
| 3 | * Copyright 2019-2024 NXP |
| 4 | * |
| 5 | * KEYWORDS: micro-power uPower driver API |
| 6 | * ----------------------------------------------------------------------------- |
| 7 | * PURPOSE: SoC-dependent uPower driver API #defines and typedefs shared |
| 8 | * with the firmware |
| 9 | * ----------------------------------------------------------------------------- |
| 10 | * PARAMETERS: |
| 11 | * PARAM NAME RANGE:DESCRIPTION: DEFAULTS: UNITS |
| 12 | * ----------------------------------------------------------------------------- |
| 13 | * REUSE ISSUES: no reuse issues |
| 14 | */ |
| 15 | |
| 16 | #ifndef UPWR_SOC_DEFS_H |
| 17 | #define UPWR_SOC_DEFS_H |
| 18 | |
| 19 | #include <stdbool.h> |
| 20 | #include <stdint.h> |
| 21 | |
| 22 | #include "upower_defs.h" |
| 23 | |
| 24 | #define UPWR_MU_MSG_SIZE (2U) /* words */ |
| 25 | |
| 26 | #ifdef NUM_PMC_SWT_WORDS |
| 27 | #define UPWR_PMC_SWT_WORDS NUM_PMC_SWT_WORDS |
| 28 | #endif |
| 29 | |
| 30 | #ifdef NUM_PMC_RAM_WORDS |
| 31 | #define UPWR_PMC_MEM_WORDS NUM_PMC_RAM_WORDS |
| 32 | #endif |
| 33 | |
| 34 | #ifndef UPWR_DRAM_SHARED_BASE_ADDR |
| 35 | #define UPWR_DRAM_SHARED_BASE_ADDR (0x28330000U) |
| 36 | #endif |
| 37 | |
| 38 | #ifndef UPWR_DRAM_SHARED_SIZE |
| 39 | #define UPWR_DRAM_SHARED_SIZE (2048U) |
| 40 | #endif |
| 41 | |
| 42 | #define UPWR_DRAM_SHARED_ENDPLUS (UPWR_DRAM_SHARED_BASE_ADDR+\ |
| 43 | UPWR_DRAM_SHARED_SIZE) |
| 44 | |
| 45 | #ifndef UPWR_API_BUFFER_BASE |
| 46 | #define UPWR_API_BUFFER_BASE (0x28330600U) |
| 47 | #endif |
| 48 | |
| 49 | #ifndef UPWR_API_BUFFER_ENDPLUS |
| 50 | #define UPWR_API_BUFFER_ENDPLUS (UPWR_DRAM_SHARED_ENDPLUS - 64U) |
| 51 | #endif |
| 52 | |
| 53 | #ifndef UPWR_PMC_SWT_WORDS |
| 54 | #define UPWR_PMC_SWT_WORDS (1U) |
| 55 | #endif |
| 56 | |
| 57 | #ifndef UPWR_PMC_MEM_WORDS |
| 58 | #define UPWR_PMC_MEM_WORDS (2U) |
| 59 | #endif |
| 60 | |
| 61 | #define UPWR_OSC_HI_FREQ (64U) // MHz |
| 62 | #define UPWR_OSC_LO_FREQ (16U) // MHz |
| 63 | |
| 64 | #ifndef UPWR_I2C_FREQ |
| 65 | #define UPWR_I2C_FREQ (UPWR_OSC_HI_FREQ * 1000000U) |
| 66 | #endif |
| 67 | |
| 68 | /* |
| 69 | * i.MX8ULP-dependent uPower API Definition |
| 70 | * |
| 71 | * This chapter documents the API definitions that are specific to the |
| 72 | * i.MX8ULP SoC. |
| 73 | * |
| 74 | */ |
| 75 | |
| 76 | /**--------------------------------------------------------------- |
| 77 | * INITIALIZATION, CONFIGURATION |
| 78 | * |
| 79 | * i.MX8ULP provides only one Message Unit (MU) for each core domain: |
| 80 | * Real Time Domain (RTD) and Application Domain (APD), which has two A35 cores. |
| 81 | * Both A35 cores in APD must share the same API instance, meaning upwr_init |
| 82 | * must be called only once for each domain. The API does not provide any |
| 83 | * mutually exclusion or locking mechanism for concurrent accesses from both |
| 84 | * APD cores, so any API arbitration, if needed, must be implemented by the |
| 85 | * API user code. |
| 86 | * |
| 87 | * A domain must not go to Power Down (PD) or Deep Power Down (DPD) power modes |
| 88 | * with any service still pending (response not received). |
| 89 | * |
| 90 | * Next sections describe the i.MX8ULP particularities of service calls. |
| 91 | * |
| 92 | */ |
| 93 | |
| 94 | /**+ |
| 95 | * upwr_start() |
| 96 | * |
| 97 | * i.MX8ULP ROM firmware provides only the launch option 0, which has no |
| 98 | * power mode transition support and provides the following services: |
| 99 | * - upwr_xcp_config |
| 100 | * - upwr_xcp_sw_alarm |
| 101 | * - upwr_pwm_param |
| 102 | * - upwr_pwm_power_on |
| 103 | * - upwr_pwm_power-off |
| 104 | * - upwr_pwm_mem_retain |
| 105 | * - upwr_pwm_chng_dom_bias |
| 106 | * - upwr_pwm_chng_mem_bias |
| 107 | * |
| 108 | * i.MX8ULP RAM firmware provides 2 launch options: |
| 109 | * |
| 110 | * 1. starts all tasks, services and power mode ones; |
| 111 | * this is the full-featured firmware option. |
| 112 | * 2. starts only the power mode tasks; services are not available with |
| 113 | * this option, and futher calls to upwr_start (from either domain) |
| 114 | * have no response; this option is mostly used to accelerate power mode |
| 115 | * mixed-signal simulations, and not intended to be used with silicon. |
| 116 | * |
| 117 | * Note: option 0 is also available if the RAM firmware is loaded. |
| 118 | */ |
| 119 | |
| 120 | /* service upwr_pwm_set_domain_pmic_rail message argument fields*/ |
| 121 | typedef struct { |
| 122 | uint32_t domain : 16U; |
| 123 | uint32_t rail : 16U; |
| 124 | } upwr_pwm_dom_pmic_rail_args; |
| 125 | |
| 126 | #define UPWR_FILL_DOMBIAS_ARGS(dom, bias, args) \ |
| 127 | do { \ |
| 128 | (args).B.domapply = (args).B.avdapply = 0U; \ |
| 129 | switch ((bias)->apply) { \ |
| 130 | case BIAS_APPLY_RTD_AVD: \ |
| 131 | (args).B.avdapply = 1U; \ |
| 132 | /* fall through */ \ |
| 133 | case BIAS_APPLY_RTD: \ |
| 134 | (dom) = (uint32_t)RTD_DOMAIN; \ |
| 135 | (args).B.domapply = 1U; \ |
| 136 | break; \ |
| 137 | case BIAS_APPLY_APD_AVD: \ |
| 138 | (args).B.avdapply = 1U; \ |
| 139 | /* fall through */ \ |
| 140 | case BIAS_APPLY_APD: \ |
| 141 | (dom) = (uint32_t)APD_DOMAIN; \ |
| 142 | (args).B.domapply = 1U; \ |
| 143 | break; \ |
| 144 | case BIAS_APPLY_AVD: \ |
| 145 | (args).B.avdapply = 1U; \ |
| 146 | break; \ |
| 147 | default: \ |
| 148 | break; \ |
| 149 | } \ |
| 150 | (args).B.dommode = (uint32_t)((bias)->dommode); \ |
| 151 | (args).B.avdmode = (uint32_t)((bias)->avdmode); \ |
| 152 | uint32_t sat = UPWR_BIAS2MILIV((1UL << UPWR_DOMBIAS_RBB_BITS) - 1UL);\ |
| 153 | (args).B.domrbbn = ((bias)->dombias.rbbn > sat) ? sat : \ |
| 154 | UPWR_BIAS_MILIV((bias)->dombias.rbbn); \ |
| 155 | (args).B.domrbbp = ((bias)->dombias.rbbp > sat) ? sat : \ |
| 156 | UPWR_BIAS_MILIV((bias)->dombias.rbbp); \ |
| 157 | (args).B.avdrbbn = ((bias)->avdbias.rbbn > sat) ? sat : \ |
| 158 | UPWR_BIAS_MILIV((bias)->avdbias.rbbn); \ |
| 159 | (args).B.avdrbbp = ((bias)->avdbias.rbbp > sat) ? sat : \ |
| 160 | UPWR_BIAS_MILIV((bias)->avdbias.rbbp); \ |
| 161 | } while (false) |
| 162 | |
| 163 | #define UPWR_FILL_MEMBIAS_ARGS(bias, args) \ |
| 164 | do { \ |
| 165 | (args).B.en = (bias)->en; \ |
| 166 | } while (false) |
| 167 | |
| 168 | |
| 169 | #define UPWR_APD_CORES (2U) |
| 170 | #define UPWR_RTD_CORES (1U) |
| 171 | |
| 172 | #define RTD_DOMAIN (0U) |
| 173 | #define APD_DOMAIN (1U) |
| 174 | #define UPWR_MAIN_DOMAINS (2U) |
| 175 | #define AVD_DOMAIN (2U) |
| 176 | #define UPWR_DOMAIN_COUNT (3U) |
| 177 | #define PSD_DOMAIN (3U) |
| 178 | #define UPWR_ALL_DOMAINS (4U) |
| 179 | |
| 180 | typedef uint32_t soc_domain_t; |
| 181 | |
| 182 | /*========================================================================= |
| 183 | * UNIT CONVERSION MACROS |
| 184 | * These macros convert physical units to the values passed as arguments |
| 185 | * in API functions. |
| 186 | *========================================================================= |
| 187 | */ |
| 188 | |
| 189 | #define UPWR_VOLT_MILIV(v) (v) /* voltage in mV to argument value */ |
| 190 | #define UPWR_VOLT_MICROV(v)((v) / 1000U) /* voltage in uV to argument value */ |
| 191 | #define UPWR_BIAS_MILIV(v) (((v) + 49UL) / 50UL) /* bias voltage(mV) to argument value */ |
| 192 | #define UPWR_BIAS2MILIV(v) ((v) * 50UL) /* inverse of UPWR_BIAS_MILIV */ |
| 193 | #define UPWR_FREQ_KHZ(f) (f) /* frequency (kHz) to argument value */ |
| 194 | |
| 195 | #define UPWR_DOMBIAS_MAX_MV (UPWR_BIAS2MILIV((1U << UPWR_DOMBIAS_RBB_BITS) - 1U)) |
| 196 | |
| 197 | /**--------------------------------------------------------------- |
| 198 | * EXCEPTION SERVICE GROUP |
| 199 | */ |
| 200 | |
| 201 | /**+ |
| 202 | * upwr_xcp_config() |
| 203 | * |
| 204 | * The i.MX8ULP uPower configuration struct contains the following bitfields: |
| 205 | * |
| 206 | * - ALARM_INT (1 bit): tells which RTD MU interrupt should be used for alarms; |
| 207 | * 1= MU GPI1; 0= MU GPI0; APD alarms always use GPI0. |
| 208 | * - CFG_IOMUX (1 bit): determintes if uPower configures i.MX8ULP IOMUX for |
| 209 | * I2C and mode pins used to control an external PMIC; |
| 210 | * 1= uPower firmware or PMIC driver configures i.MX8ULP IOMUX and mode pins; |
| 211 | * 0= i.MX8ULP IOMUX and mode pins not configured by uPower; |
| 212 | * - DGNBUFBITS (4 bits): determines the diagnostic buffer size according to |
| 213 | * the formula: size = 2^(DGNBUFBITS+3) bytes; |
| 214 | * |
| 215 | * Defaults are all zeroes; all other bits are reserved, and must be written 0. |
| 216 | */ |
| 217 | |
| 218 | typedef union { |
| 219 | uint32_t R; |
| 220 | struct { |
| 221 | uint32_t ALARM_INT : 1U; |
| 222 | uint32_t CFG_IOMUX : 1U; |
| 223 | uint32_t DGNBUFBITS : 4U; |
| 224 | uint32_t RSV : 26U; |
| 225 | } B; |
| 226 | } upwr_xcp_config_t; |
| 227 | |
| 228 | /**+ |
| 229 | * upwr_xcp_sw_alarm() |
| 230 | * |
| 231 | * Argument code is defined by the enum upwr_alarm_t, with the values: |
| 232 | * - UPWR_ALARM_INTERNAL: internal software error |
| 233 | * - UPWR_ALARM_EXCEPTION: uPower core exception, either illegal instruction or |
| 234 | * bus error |
| 235 | * - UPWR_ALARM_SLACK: delay path too slow, meaning a timing violation occurred |
| 236 | * or is iminent. |
| 237 | * - UPWR_ALARM_VOLTAGE: one of the measured voltages is below safety margins. |
| 238 | * |
| 239 | * Note that this service emulates an alarm that would normally be issued by |
| 240 | * uPower when it detects one of the causes above. A request to alarm the APD |
| 241 | * domain when it is powered off returns success, but is ineffective. |
| 242 | * |
| 243 | */ |
| 244 | |
| 245 | #define UPWR_ALARM_INTERNAL (0U) /* internal error */ |
| 246 | #define UPWR_ALARM_EXCEPTION (1U) /* core exception */ |
| 247 | #define UPWR_ALARM_SLACK (2U) /* delay path too slow */ |
| 248 | #define UPWR_ALARM_VOLTAGE (3U) /* voltage drop */ |
| 249 | #define UPWR_ALARM_LAST UPWR_ALARM_VOLTAGE |
| 250 | |
| 251 | typedef uint32_t upwr_alarm_t; |
| 252 | |
| 253 | /**--------------------------------------------------------------- |
| 254 | * POWER MANAGEMENT SERVICE GROUP |
| 255 | */ |
| 256 | |
| 257 | /* values in mV: */ |
| 258 | #define UPWR_RTD_RBBN_MAX (1300U) /* max. RTD Reverse Back Bias N-Well */ |
| 259 | #define UPWR_RTD_RBBN_MIN (100U) /* min. RTD Reverse Back Bias N-Well */ |
| 260 | |
| 261 | #define UPWR_RTD_RBBP_MAX (1300U) /* max. RTD Reverse Back Bias P-Well */ |
| 262 | #define UPWR_RTD_RBBP_MIN (100U) /* min. RTD Reverse Back Bias P-Well */ |
| 263 | |
| 264 | /* APD bias can only two values (mV): */ |
| 265 | #define UPWR_APD_RBBN_LO (1000U) /* low APD Reverse Back Bias N-Well */ |
| 266 | #define UPWR_APD_RBBN_HI (1300U) /* high APD Reverse Back Bias N-Well */ |
| 267 | |
| 268 | #define UPWR_APD_RBBP_LO (1000U) /* low APD Reverse Back Bias P-Well */ |
| 269 | #define UPWR_APD_RBBP_HI (1300U) /* high APD Reverse Back Bias P-Well */ |
| 270 | |
| 271 | /* AVD bias can only two values (mV): */ |
| 272 | #define UPWR_AVD_RBBN_LO (1000U) /* low AVD Reverse Back Bias N-Well */ |
| 273 | #define UPWR_AVD_RBBN_HI (1300U) /* high AVD Reverse Back Bias N-Well */ |
| 274 | |
| 275 | #define UPWR_AVD_RBBP_LO (1000U) /* low AVD Reverse Back Bias P-Well */ |
| 276 | #define UPWR_AVD_RBBP_HI (1300U) /* high AVD Reverse Back Bias P-Well */ |
| 277 | |
| 278 | /**+ |
| 279 | * upwr_pwm_param() |
| 280 | * |
| 281 | * Argument param is defined by the struct/union upwr_pwm_param_t with the |
| 282 | * following i.MX8ULP-specific bitfields: |
| 283 | * - DPD_ALLOW (1 bit): 1= allows uPower power mode to go Deep Power Down (DPD); |
| 284 | * uPower DPD also depends on other conditions, but if this bit is 0 uPower |
| 285 | * won't go DPD even if those conditions are met; it can go either Sleep or |
| 286 | * Deep Sleep (DSL) depending on the other configurations. |
| 287 | * - DSL_DIS (1 bit): if this bit is 1, uPower power mode won't go Deep Sleep |
| 288 | * (DSL) even if the other conditions for that are met; |
| 289 | * it may go Sleep instead. |
| 290 | * - SLP_ALLOW (1 bit): if this bit is 1, uPower power mode will go Sleep if |
| 291 | * the conditions for Partial Active are met; it may also go Deep Sleep if bit |
| 292 | * DSL_DIS=1. |
| 293 | * - DSL_BGAP_OFF (1 bit): 1= turns bandgap off when uPower goes Deep Sleep; |
| 294 | * 0= leaves bandgap on when uPower goes Deep Sleep (DSL). |
| 295 | * - DPD_BGAP_ON (1 bit): 1= leaves bandgap on when uPower goes Deep Power Down |
| 296 | * (DPD); 0= powers off bandgap when uPower goes Deep Power Down (DPD). |
| 297 | * |
| 298 | * Defaults are all zeroes; all other bits are reserved, and must be written 0. |
| 299 | */ |
| 300 | |
| 301 | typedef union { |
| 302 | uint32_t R; |
| 303 | struct { |
| 304 | uint32_t DPD_ALLOW : 1U; |
| 305 | uint32_t DSL_DIS : 1U; |
| 306 | uint32_t SLP_ALLOW : 1U; |
| 307 | uint32_t DSL_BGAP_OFF : 1U; |
| 308 | uint32_t DPD_BGAP_ON : 1U; |
| 309 | uint32_t RSV : 27U; |
| 310 | } B; |
| 311 | } upwr_pwm_param_t; |
| 312 | |
| 313 | /**+ |
| 314 | * upwr_pwm_chng_reg_voltage() |
| 315 | * |
| 316 | * Argument reg is defined by the enum upwr_pmc_reg_t, with regulator ids: |
| 317 | * - RTD_PMC_REG: RTD regulator |
| 318 | * - APD_PMC_REG: APD regulator |
| 319 | * - RTD_BIAS_PMC_REG: RTD bias regulator |
| 320 | * - APD_BIAS_PMC_REG: APD bias regulator |
| 321 | * - RTD_LVD_PMC_MON: RTD LVD regulator |
| 322 | * - APD_LVD_PMC_MON: APD LVD regulator |
| 323 | * - AVD_LVD_PMC_MON: AVD LVD regulator |
| 324 | * |
| 325 | * Argument volt is defined by the formula: |
| 326 | * |
| 327 | * argument = 92.30797633*V - 55.000138, rounded to the nearest integer, |
| 328 | * where V is the value in Volts, with a minimum of 0.595833 V (argument = 0). |
| 329 | * |
| 330 | */ |
| 331 | |
| 332 | /* Regulator ids */ |
| 333 | typedef enum { |
| 334 | RTD_PMC_REG, |
| 335 | APD_PMC_REG, |
| 336 | RTD_BIAS_PMC_REG, |
| 337 | APD_BIAS_PMC_REG, |
| 338 | RTD_LVD_PMC_MON, |
| 339 | APD_LVD_PMC_MON, |
| 340 | AVD_LVD_PMC_MON |
| 341 | } upwr_pmc_reg_t; |
| 342 | |
| 343 | /**+ |
| 344 | * upwr_pwm_freq_setup() |
| 345 | * |
| 346 | * Argument domain is either RTD_DOMAIN or APD_DOMAIN. |
| 347 | * Arguments nextfq and currfq are to be defined (TBD). |
| 348 | */ |
| 349 | |
| 350 | /**+ |
| 351 | * upwr_pwm_dom_power_on() |
| 352 | * |
| 353 | * The arguments must comply with the restrictions below, otherwise the service |
| 354 | * is not executed and returns error UPWR_RESP_BAD_REQ: |
| 355 | * - argument domain can only be APD_DOMAIN, because in i.MX8ULP it is not |
| 356 | * possible APD powered on (calling the service) with RTD completely |
| 357 | * powered off. |
| 358 | * - the call can only be made from the RTD domain, for the same reason. |
| 359 | * - argument boot can only be 1, because in i.MX8ULP it is not possible to |
| 360 | * power on the APD domain without starting the core boot. |
| 361 | * |
| 362 | * If APD is already powered on and booting/booted when the service is called, |
| 363 | * it returns success without doing anything. |
| 364 | */ |
| 365 | |
| 366 | /**+ |
| 367 | * upwr_pwm_boot_start() |
| 368 | * |
| 369 | * The arguments must comply with the restrictions below, otherwise the service |
| 370 | * is not executed and returns error UPWR_RESP_BAD_REQ: |
| 371 | * - argument domain can only be APD_DOMAIN, because in i.MX8ULP it is not |
| 372 | * possible APD powered on (calling the service) with RTD completely |
| 373 | * powered off. |
| 374 | * - the call can only be made from the RTD domain, for the same reason. |
| 375 | * |
| 376 | * If APD is already booted when the service is called, it returns success |
| 377 | * without doing anything. Otherwise, it returns the error UPWR_RESP_BAD_STATE, |
| 378 | * because in i.MX8ULP APD cannot be booted separately from power on. |
| 379 | */ |
| 380 | |
| 381 | /**+ |
| 382 | * upwr_pwm_power_on(), |
| 383 | * upwr_pwm_power_off(), |
| 384 | * upwr_pwm_mem_retain() |
| 385 | * |
| 386 | * These three service functions use the same arguments: |
| 387 | * |
| 388 | * argument swt is an array of one 32-bit word: uint32_t swt[1]; |
| 389 | * naturally the pointer to a single uint32_t variable may be passed. |
| 390 | * Each bit of the word corresponds to a switch, according to the i.MX8ULP |
| 391 | * Reference Manual Rev B draft 2 table 64 Power switch reset state, |
| 392 | * and the following formula: |
| 393 | * |
| 394 | * if switch number < 10 bit number = switch number; |
| 395 | * if switch number > 9 bit number = switch number + 3; |
| 396 | * |
| 397 | * bits 9, 10, 11 and 12 must have the same value (corresponding to switch 9) |
| 398 | * |
| 399 | * Note: this argument is not used in upwr_pwm_mem_retain. |
| 400 | * |
| 401 | * argument mem is an array of two 32-bit words: uint32_t mem[2]; |
| 402 | * naturally the pointer to a single uint64_t variable may be passed, since |
| 403 | * both ARM and RISC-V are little endian architectures. |
| 404 | * Each bit of the words corresponds to a memory, according to the i.MX8ULP |
| 405 | * Reference Manual table "Memory Partitions". |
| 406 | * |
| 407 | * Turning a memory completely on (array and peripheral) will automatically |
| 408 | * turn on its power switch, even if not explicitly commanded. |
| 409 | * Turning a memory's power switch off will automatically turn off its array |
| 410 | * and peripheral beforehand, even if not explicitly commanded. |
| 411 | * |
| 412 | * Argument restrictions: |
| 413 | * |
| 414 | * The swt and mem arguments must comply with the restrictions below, otherwise |
| 415 | * the service is not executed (no switch/memory is changed) and returns error |
| 416 | * UPWR_RESP_BAD_REQ: |
| 417 | * 1. one must not put a memory in retention coming from an off state. |
| 418 | * 2. switches 9, 10, 11 and 12 must be turned on/off simultaneously. |
| 419 | * 3. an AVD switch can only be turned off if all AVD switches belong to the |
| 420 | * domain requesting the service (as defined by registers SYSCTRL0, |
| 421 | * LPAV_MASTER_ALLOC_CTRL and LPAV_SLAVE_ALLOC_CTRL); |
| 422 | * there is no such restriction to turn the switch on. |
| 423 | * 4. an AVD memory can only be turned off or put in retention if all |
| 424 | * AVD memories belong to the domain requesting the service |
| 425 | * (as defined by registers SYSCTRL0, LPAV_MASTER_ALLOC_CTRL and |
| 426 | * LPAV_SLAVE_ALLOC_CTRL); there is no such restriction to turn on the |
| 427 | * memories. |
| 428 | * 5. EdgeLock RAMs must not be turned off, unless RTD domain is in |
| 429 | * Deep Power Down (DPD). |
| 430 | * 6. Power Switch 19 must be on to turn on switches 17 (MIPI/DSI), |
| 431 | * 18 (MIPI/CSI), and all AVD power switches. |
| 432 | * |
| 433 | * Service Errors: |
| 434 | * |
| 435 | * Besides the error UPWR_RESP_BAD_REQ caused by violations of the restrictions |
| 436 | * above, the services may fail with error UPWR_RESP_RESOURCE if a power mode |
| 437 | * transition or a similar service is executing at the same time. |
| 438 | * This error should be interpreted as a "try later" response, as the service |
| 439 | * will succeed once those concurrent executions are done, and no other is |
| 440 | * started. |
| 441 | */ |
| 442 | |
| 443 | /**+ |
| 444 | * upwr_pwm_chng_switch_mem() |
| 445 | * |
| 446 | * The bit numbers in the argument struct mask and on/off state fields |
| 447 | * are the same as for services upwr_pwm_power_on, upwr_pwm_power_off and |
| 448 | * upwr_pwm_mem_retain. |
| 449 | * |
| 450 | * Turning a memory completely on (array and peripheral) will automatically |
| 451 | * turn on its power switch, even if not explicitly commanded. |
| 452 | * |
| 453 | * Argument restrictions: |
| 454 | * |
| 455 | * Same argument restrictions as services upwr_pwm_power_on, upwr_pwm_power_off |
| 456 | * and upwr_pwm_mem_retain, plus the following: |
| 457 | * |
| 458 | * 1. one must not turn a memory peripheral on and a memory array off. |
| 459 | * 2. one must not put a memory in retention and switch its power switch off. |
| 460 | * |
| 461 | * Service Errors: |
| 462 | * |
| 463 | * Besides the error UPWR_RESP_BAD_REQ caused by violations of the restrictions |
| 464 | * above, the service may fail with error UPWR_RESP_RESOURCE if a power mode |
| 465 | * transition or a similar service is executing at the same time. |
| 466 | * This error should be interpreted as a "try later" response, as the service |
| 467 | * will succeed once those concurrent executions are done, and no other is |
| 468 | * started. |
| 469 | */ |
| 470 | |
| 471 | /**+ |
| 472 | * upwr_pwm_pmode_config() |
| 473 | * |
| 474 | * The same power switch and memory restrictions of service |
| 475 | * upwr_pwm_chng_switch_mem apply between power modes, however they are not |
| 476 | * enforced by this service, that is, it does not return service error. |
| 477 | * |
| 478 | * The default power mode configurations for RTD and APD are documented in the |
| 479 | * i.MX8ULP Reference Manual sections "Power mode details (real-time domain)" |
| 480 | * and "Power mode details (application domain)", respectively. |
| 481 | * If those configurations are satisfactory, this service does not have |
| 482 | * to be called. |
| 483 | * |
| 484 | * Power Mode Configuration Structure: |
| 485 | * |
| 486 | * Follows a description of the power mode configuration structure elements. |
| 487 | * - dom_swts: the same switch configuration structures used in service |
| 488 | * upwr_pwm_chng_switch_mem argument swt. |
| 489 | * - mem_swts: the same memory configuration structures used in service |
| 490 | * upwr_pwm_chng_switch_mem argument mem. |
| 491 | * - regs: an array of structs base_reg_cfg_t (see upower_soc_defs.h), |
| 492 | * one element for each regulator; base_reg_cfg_t has fields |
| 493 | * mode (regulator-dependent), lvl (voltage level in uV), |
| 494 | * comp (regulator-dependent complamentary info). |
| 495 | * - pads: pad configuration in low power; see pad_cfg_t definition below. |
| 496 | * - mons: domain monitors (LVD and HVD) configuration; |
| 497 | * see mon_cfg_t definition below. |
| 498 | * - avd_mons: same as mons for the AVD domain; see mon_cfg_t definition below. |
| 499 | * - dom_bbias: back-bias configuration for the domain; |
| 500 | * see base_bbias_cfg_t definition below. |
| 501 | * - avd_bbias: back-bias configuration for the AVD domain; |
| 502 | * see base_bbias_cfg_t definition below. |
| 503 | * - mem_bbias: back-bias configuration for the memory; |
| 504 | * see base_bbias_cfg_t definition below. |
| 505 | * - mem_fbias: forward-bias configuration for the memory; |
| 506 | * see base_fbias_cfg_t definition below. |
| 507 | * - pmic: PMIC-specific configuration |
| 508 | * |
| 509 | * Structure pad_cfg_t: |
| 510 | * |
| 511 | * Pad control for low power modes (power off, etc), 1 bit per pad segment. |
| 512 | * - rst : put pad segment in reset. |
| 513 | * - iso : put pad segment in isolation. |
| 514 | * - compl: specific pad segment information. |
| 515 | * - msk : select which pads will be updated. |
| 516 | * |
| 517 | * Structure mon_cfg_t: |
| 518 | * |
| 519 | * Configures a voltage monitor and its actions. |
| 520 | * There are monitors for RTD, APD and AVD, monitoring LVD and HVD. |
| 521 | * - lvl : Voltage level (in uV). |
| 522 | * - mode : Mode of monitor (ON, OFF, LP, etc). |
| 523 | * - compl: Extra info for the monitor. |
| 524 | * |
| 525 | * Structure base_bbias_cfg_t: |
| 526 | * |
| 527 | * Configures back-bias (for domain or memory). |
| 528 | * - mode : Back bias mode (OFF, RBB, ARBB, etc). |
| 529 | * - p_lvl: Voltage level of p-well (in mV). |
| 530 | * - n_lvl: Voltage level of n-well (in mV). |
| 531 | * - compl: Complementary bias-specific (enable reset, interrupt, clamp, etc). |
| 532 | * |
| 533 | * Structure base_fbias_cfg_t: |
| 534 | * |
| 535 | * Configure memory forward bias for a memory segment. |
| 536 | * |
| 537 | * - mode : Forward bias mode (OFF, ON). |
| 538 | * - msk : Selects which memory will be updated |
| 539 | * |
| 540 | */ |
| 541 | |
| 542 | /*========================================================================= |
| 543 | * Domain bias |
| 544 | *========================================================================= |
| 545 | */ |
| 546 | |
| 547 | /**+ |
| 548 | * upwr_pwm_chng_dom_bias() |
| 549 | * |
| 550 | * Argument bias is a pointer to a struct with fields: |
| 551 | * - apply: tells to which domains the bias must be applied; |
| 552 | * options are RTD only (BIAS_APPLY_RTD), RTD and AVD (BIAS_APPLY_RTD_AVD), |
| 553 | * APD only (BIAS_APPLY_APD), APD and AVD (BIAS_APPLY_APD_AVD), |
| 554 | * AVD only (BIAS_APPLY_AVD) |
| 555 | * - dommode: bias mode of the main domain (RTD or APD, determined by apply); |
| 556 | * options are disabled (NBB_BIAS_MODE), reverse back bias (RBB_BIAS_MODE), |
| 557 | * asymmetrical forward bias (AFBB_BIAS_MODE), asymmetrical reverse bias |
| 558 | * (ARBB_BIAS_MODE). |
| 559 | * - avdmode: bias mode of Audio-Video Domain (AVD); |
| 560 | * options are the same as dommode. |
| 561 | * - dombias: bias voltage level(s) for the main domain (RTD or APD, |
| 562 | * determined by apply); it is a structure with 2 fields, rbbn and rbbp, |
| 563 | * for the N-well and P-well voltages, respectively; values are in mV. |
| 564 | * - avdbias: bias voltage level(s) for the Audio-Video Domain (AVD); |
| 565 | * same fields as dombias; |
| 566 | * |
| 567 | * Argument restrictions: |
| 568 | * |
| 569 | * Voltage levels must comply with the #define-determined limits/options: |
| 570 | * between UPWR_RTD_RBBN_MIN and UPWR_RTD_RBBN_MAX (inclusive) for RTD N-well; |
| 571 | * between UPWR_RTD_RBBP_MIN and UPWR_RTD_RBBP_MAX (inclusive) for RTD P-well; |
| 572 | * either UPWR_APD_RBBN_LO or UPWR_APD_RBBN_HI for APD N-well; |
| 573 | * either UPWR_APD_RBBP_LO or UPWR_APD_RBBP_HI for APD P-well; |
| 574 | * either UPWR_AVD_RBBN_LO or UPWR_AVD_RBBN_HI for AVD N-well; |
| 575 | * either UPWR_AVD_RBBP_LO or UPWR_AVD_RBBP_HI for AVD P-well; |
| 576 | * |
| 577 | * But note that the limits/options above do not apply to all bias modes: |
| 578 | * rbbn is used and checked only in mode RBB_BIAS_MODE; |
| 579 | * rbbp is used and checked only in modes RBB_BIAS_MODE and ARBB_BIAS_MODE; |
| 580 | * modes AFBB_BIAS_MODE and NBB_BIAS_MODE use or check neither rbbn nor rbbp; |
| 581 | * |
| 582 | * Service error UPWR_RESP_BAD_REQ is returned if the voltage limits/options |
| 583 | * above are violated. |
| 584 | */ |
| 585 | |
| 586 | /* argument struct for service upwr_pwm_chng_dom_bias: |
| 587 | */ |
| 588 | |
| 589 | typedef enum { /* bias modes (both domain and memory): */ |
| 590 | NBB_BIAS_MODE = 0, /* bias disabled */ |
| 591 | RBB_BIAS_MODE = 1, /* reverse back bias enabled */ |
| 592 | AFBB_BIAS_MODE = 2, /* asymmetrical forward bias */ |
| 593 | ARBB_BIAS_MODE = 3 /* asymmetrical reverse bias */ |
| 594 | } upwr_bias_mode_t; |
| 595 | |
| 596 | /* Domain Bias config (one per domain) */ |
| 597 | |
| 598 | typedef enum { |
| 599 | BIAS_APPLY_RTD, /* apply to RTD only */ |
| 600 | BIAS_APPLY_RTD_AVD, /* apply to RTD and AVD */ |
| 601 | BIAS_APPLY_APD, /* apply to APD only */ |
| 602 | BIAS_APPLY_APD_AVD, /* apply to APD and AVD */ |
| 603 | BIAS_APPLY_AVD, /* apply to AVD only */ |
| 604 | BIAS_APPLY_COUNT /* number of apply options */ |
| 605 | } upwr_bias_apply_t; |
| 606 | |
| 607 | typedef struct { |
| 608 | uint16_t rbbn; /* reverse back bias N well (mV) */ |
| 609 | uint16_t rbbp; /* reverse back bias P well (mV) */ |
| 610 | } upwr_rbb_t; |
| 611 | |
| 612 | struct upwr_dom_bias_cfg_t { |
| 613 | upwr_bias_apply_t apply; /* bias application option */ |
| 614 | upwr_bias_mode_t dommode; /* RTD/APD bias mode config */ |
| 615 | upwr_bias_mode_t avdmode; /* AVD bias mode config */ |
| 616 | upwr_rbb_t dombias; /* RTD/APD reverse back bias */ |
| 617 | upwr_rbb_t avdbias; /* AVD reverse back bias */ |
| 618 | }; |
| 619 | |
| 620 | /* bias struct used in power mode config definitions */ |
| 621 | |
| 622 | /** |
| 623 | * When write power mode transition program, please read below comments carefully. |
| 624 | * The structure and logic is complex, There is a lot of extension and reuse. |
| 625 | * |
| 626 | * First, for mode, extend "uint32_t mode" to a union struct, add support for AVD: |
| 627 | * typedef union { |
| 628 | * uint32_t R; |
| 629 | * struct { |
| 630 | * uint32_t mode : 8; |
| 631 | * uint32_t rsrv_1 : 8; |
| 632 | * uint32_t avd_mode : 8; |
| 633 | * uint32_t rsrv_2 : 8; |
| 634 | * } B; |
| 635 | * } dom_bias_mode_cfg_t; |
| 636 | |
| 637 | Second, if mode is AFBB mode, no need to configure rbbn and rbbp, uPower firmware |
| 638 | will configure all SRAM_AFBB_0 or SRAM_AFBB_1 for corresponding domain. |
| 639 | |
| 640 | Third, if mode is RBB mode, extend "uint32_t rbbn" and "uint32_t rbbp" to a union |
| 641 | struct, add support for AVD: |
| 642 | typedef union { |
| 643 | uint32_t R; |
| 644 | struct { |
| 645 | uint32_t lvl : 8; |
| 646 | uint32_t rsrv_1 : 8; |
| 647 | uint32_t avd_lvl : 8; |
| 648 | uint32_t rsrv_2 : 8; |
| 649 | } B; |
| 650 | } dom_bias_lvl_cfg_t; |
| 651 | |
| 652 | * |
| 653 | */ |
| 654 | typedef struct { |
| 655 | uint32_t mode; /* Domain bias mode config, extend to dom_bias_mode_cfg_t to support RTD, APD, AVD */ |
| 656 | uint32_t rbbn; /* reverse back bias N well */ |
| 657 | uint32_t rbbp; /* reverse back bias P well */ |
| 658 | } UPWR_DOM_BIAS_CFG_T; |
| 659 | |
| 660 | /*========================================================================= |
| 661 | * Memory bias |
| 662 | *========================================================================= |
| 663 | */ |
| 664 | /**+ |
| 665 | * upwr_pwm_chng_mem_bias() |
| 666 | * |
| 667 | * Argument struct contains only the field en, which can be either 1 (bias |
| 668 | * enabled) or 0 (bias disabled). |
| 669 | * |
| 670 | * Argument domain must be either RTD_DOMAIN (Real Time Domain) or APD_DOMAIN |
| 671 | * (Application Domain). |
| 672 | */ |
| 673 | |
| 674 | /* Memory Bias config */ |
| 675 | struct upwr_mem_bias_cfg_t { |
| 676 | uint32_t en; /* Memory bias enable config */ |
| 677 | }; |
| 678 | |
| 679 | /* bias struct used in power mode config definitions */ |
| 680 | typedef struct { |
| 681 | uint32_t en; /* Memory bias enable config */ |
| 682 | } UPWR_MEM_BIAS_CFG_T; |
| 683 | |
| 684 | /* Split different Bias */ |
| 685 | struct upwr_pmc_bias_cfg_t { |
| 686 | UPWR_DOM_BIAS_CFG_T dombias_cfg; /* Domain Bias config */ |
| 687 | UPWR_MEM_BIAS_CFG_T membias_cfg; /* Memory Bias config */ |
| 688 | }; |
| 689 | |
| 690 | /*========================================================================= |
| 691 | * Power modes |
| 692 | *========================================================================= |
| 693 | */ |
| 694 | |
| 695 | /* from msb->lsb: Azure bit, dual boot bit, low power boot bit */ |
| 696 | typedef enum { |
| 697 | SOC_BOOT_SINGLE = 0, |
| 698 | SOC_BOOT_LOW_PWR = 1, |
| 699 | SOC_BOOT_DUAL = 2, |
| 700 | SOC_BOOT_AZURE = 4 |
| 701 | } SOC_BOOT_TYPE_T; |
| 702 | |
| 703 | #ifdef UPWR_COMP_RAM |
| 704 | /* Power modes for RTD domain */ |
| 705 | typedef enum { |
| 706 | DPD_RTD_PWR_MODE, /* Real Time Deep Power Down mode */ |
| 707 | PD_RTD_PWR_MODE, /* Real Time Power Down mode */ |
| 708 | DSL_RTD_PWR_MODE, /* Real Time Domain Deep Sleep Mode */ |
| 709 | HLD_RTD_PWR_MODE, /* Real Time Domain Hold Mode */ |
| 710 | SLP_RTD_PWR_MODE, /* Sleep Mode */ |
| 711 | ADMA_RTD_PWR_MODE,/* Active DMA Mode */ |
| 712 | ACT_RTD_PWR_MODE, /* Active Domain Mode */ |
| 713 | NUM_RTD_PWR_MODES |
| 714 | } upwr_ps_rtd_pwr_mode_t; |
| 715 | |
| 716 | /* Abstract power modes */ |
| 717 | typedef enum { |
| 718 | DPD_PWR_MODE, |
| 719 | PD_PWR_MODE, |
| 720 | PACT_PWR_MODE, |
| 721 | DSL_PWR_MODE, |
| 722 | HLD_PWR_MODE, |
| 723 | SLP_PWR_MODE, |
| 724 | ADMA_PWR_MODE, |
| 725 | ACT_PWR_MODE, |
| 726 | NUM_PWR_MODES, |
| 727 | NUM_APD_PWR_MODES = NUM_PWR_MODES, |
| 728 | TRANS_PWR_MODE = NUM_PWR_MODES, |
| 729 | INVALID_PWR_MODE = TRANS_PWR_MODE + 1 |
| 730 | } abs_pwr_mode_t; |
| 731 | #else /* UPWR_COMP_RAM */ |
| 732 | /* Power modes for RTD domain */ |
| 733 | #define DPD_RTD_PWR_MODE (0U) /* Real Time Deep Power Down mode */ |
| 734 | #define PD_RTD_PWR_MODE (1U) /* Real Time Power Down mode */ |
| 735 | #define DSL_RTD_PWR_MODE (2U) /* Real Time Domain Deep Sleep Mode */ |
| 736 | #define HLD_RTD_PWR_MODE (3U) /* Real Time Domain Hold Mode */ |
| 737 | #define SLP_RTD_PWR_MODE (4U) /* Sleep Mode */ |
| 738 | #define ADMA_RTD_PWR_MODE (5U) /* Active DMA Mode */ |
| 739 | #define ACT_RTD_PWR_MODE (6U) /* Active Domain Mode */ |
| 740 | #define NUM_RTD_PWR_MODES (7U) |
| 741 | |
| 742 | typedef uint32_t upwr_ps_rtd_pwr_mode_t; |
| 743 | |
| 744 | /* Abstract power modes */ |
| 745 | #define DPD_PWR_MODE (0U) |
| 746 | #define PD_PWR_MODE (1U) |
| 747 | #define PACT_PWR_MODE (2U) |
| 748 | #define DSL_PWR_MODE (3U) |
| 749 | #define HLD_PWR_MODE (4U) |
| 750 | #define SLP_PWR_MODE (5U) |
| 751 | #define ADMA_PWR_MODE (6U) |
| 752 | #define ACT_PWR_MODE (7U) |
| 753 | #define NUM_PWR_MODES (8U) |
| 754 | #define NUM_APD_PWR_MODES NUM_PWR_MODES |
| 755 | #define TRANS_PWR_MODE NUM_PWR_MODES |
| 756 | #define INVALID_PWR_MODE (TRANS_PWR_MODE + 1U) |
| 757 | |
| 758 | typedef uint32_t abs_pwr_mode_t; |
| 759 | #endif /* UPWR_COMP_RAM */ |
| 760 | |
| 761 | typedef struct { |
| 762 | abs_pwr_mode_t mode; |
| 763 | bool ok; |
| 764 | } pch_trans_t; |
| 765 | |
| 766 | typedef pch_trans_t rtd_trans_t; |
| 767 | |
| 768 | typedef struct { |
| 769 | abs_pwr_mode_t mode; |
| 770 | pch_trans_t core[UPWR_APD_CORES]; |
| 771 | } apd_trans_t; |
| 772 | |
| 773 | /* Codes for APD pwr mode as programmed in LPMODE reg */ |
| 774 | typedef enum { |
| 775 | ACT_APD_LPM, |
| 776 | SLP_APD_LPM = 1, |
| 777 | DSL_APD_LPM = 3, |
| 778 | PACT_APD_LPM = 7, |
| 779 | PD_APD_LPM = 15, |
| 780 | DPD_APD_LPM = 31, |
| 781 | HLD_APD_LPM = 63 |
| 782 | } upwr_apd_lpm_t; |
| 783 | |
| 784 | /* PowerSys low power config */ |
| 785 | struct upwr_powersys_cfg_t { |
| 786 | uint32_t lpm_mode; /* Powersys low power mode */ |
| 787 | }; |
| 788 | |
| 789 | /*=************************************************************************* |
| 790 | * RTD |
| 791 | *=*************************************************************************/ |
| 792 | /* Config pmc PADs */ |
| 793 | struct upwr_pmc_pad_cfg_t { |
| 794 | uint32_t pad_close; /* PMC PAD close config */ |
| 795 | uint32_t pad_reset; /* PMC PAD reset config */ |
| 796 | uint32_t pad_tqsleep; /* PMC PAD TQ Sleep config */ |
| 797 | }; |
| 798 | |
| 799 | /* Config regulator (internal and external) */ |
| 800 | struct upwr_reg_cfg_t { |
| 801 | uint32_t volt; /* Regulator voltage config */ |
| 802 | uint32_t mode; /* Regulator mode config */ |
| 803 | }; |
| 804 | |
| 805 | /* Config pmc monitors */ |
| 806 | struct upwr_pmc_mon_cfg_t { |
| 807 | uint32_t mon_hvd_en; /* PMC mon HVD */ |
| 808 | uint32_t mon_lvd_en; /* PMC mon LVD */ |
| 809 | uint32_t mon_lvdlvl; /* PMC mon LVDLVL */ |
| 810 | }; |
| 811 | |
| 812 | /* Same monitor config for RTD (for compatibility) */ |
| 813 | #define upwr_pmc_mon_rtd_cfg_t upwr_pmc_mon_cfg_t |
| 814 | |
| 815 | typedef swt_config_t ps_rtd_swt_cfgs_t[NUM_RTD_PWR_MODES]; |
| 816 | typedef swt_config_t ps_apd_swt_cfgs_t[NUM_APD_PWR_MODES]; |
| 817 | |
| 818 | /*=************************************************************************* |
| 819 | * APD |
| 820 | *=*************************************************************************/ |
| 821 | |
| 822 | /* PowerSys PMIC config */ |
| 823 | struct upwr_pmic_cfg_t { |
| 824 | uint32_t volt; |
| 825 | uint32_t mode; |
| 826 | uint32_t mode_msk; |
| 827 | }; |
| 828 | |
| 829 | typedef uint32_t offs_t; |
| 830 | |
| 831 | struct ps_apd_pwr_mode_cfg_t { |
| 832 | #ifdef UPWR_SIMULATOR_ONLY |
| 833 | struct upwr_switch_board_t *swt_board_offs; |
| 834 | struct upwr_mem_switches_t *swt_mem_offs; |
| 835 | #else |
| 836 | offs_t swt_board_offs; |
| 837 | offs_t swt_mem_offs; |
| 838 | #endif |
| 839 | struct upwr_pmic_cfg_t pmic_cfg; |
| 840 | struct upwr_pmc_pad_cfg_t pad_cfg; |
| 841 | struct upwr_pmc_bias_cfg_t bias_cfg; |
| 842 | }; |
| 843 | |
| 844 | /* Get the pointer to swt config */ |
| 845 | static inline struct upwr_switch_board_t* |
| 846 | get_apd_swt_cfg(volatile struct ps_apd_pwr_mode_cfg_t *cfg) |
| 847 | { |
| 848 | char *ptr; |
| 849 | |
| 850 | ptr = (char *)cfg; |
| 851 | ptr += (uint64_t)cfg->swt_board_offs; |
| 852 | return (struct upwr_switch_board_t *)ptr; |
| 853 | } |
| 854 | |
| 855 | /* Get the pointer to mem config */ |
| 856 | static inline struct upwr_mem_switches_t* |
| 857 | get_apd_mem_cfg(volatile struct ps_apd_pwr_mode_cfg_t *cfg) |
| 858 | { |
| 859 | char *ptr; |
| 860 | |
| 861 | ptr = (char *)cfg; |
| 862 | ptr += (uint64_t)cfg->swt_mem_offs; |
| 863 | return (struct upwr_mem_switches_t *)ptr; |
| 864 | } |
| 865 | |
| 866 | /* Power Mode configuration */ |
| 867 | |
| 868 | #define ps_rtd_pwr_mode_cfg_t upwr_power_mode_cfg_t |
| 869 | |
| 870 | /* these typedefs are just for RISC-V sizeof purpose */ |
| 871 | typedef uint32_t swt_board_ptr_t; |
| 872 | typedef uint32_t swt_mem_ptr_t; |
| 873 | |
| 874 | struct upwr_power_mode_cfg_t { |
| 875 | #ifdef UPWR_SIMULATOR_ONLY |
| 876 | struct upwr_switch_board_t *swt_board; /* Swt board for mem. */ |
| 877 | struct upwr_mem_switches_t *swt_mem; /* Swt to mem. arrays, perif */ |
| 878 | #else |
| 879 | #ifdef __LP64__ |
| 880 | uint32_t swt_board; |
| 881 | uint32_t swt_mem; |
| 882 | #else |
| 883 | struct upwr_switch_board_t *swt_board; /* Swt board for mem. */ |
| 884 | struct upwr_mem_switches_t *swt_mem; /* Swt to mem. arrays, perif */ |
| 885 | #endif |
| 886 | #endif |
| 887 | struct upwr_reg_cfg_t in_reg_cfg; /* internal regulator config*/ |
| 888 | struct upwr_reg_cfg_t pmic_cfg; /* external regulator - pmic*/ |
| 889 | struct upwr_pmc_pad_cfg_t pad_cfg; /* Pad conf for power trans*/ |
| 890 | struct upwr_pmc_mon_rtd_cfg_t mon_cfg; /*monitor configuration */ |
| 891 | struct upwr_pmc_bias_cfg_t bias_cfg; /* Memory/Domain Bias conf */ |
| 892 | struct upwr_powersys_cfg_t pwrsys_lpm_cfg; /* pwrsys low power config*/ |
| 893 | }; |
| 894 | |
| 895 | static inline unsigned int upwr_sizeof_pmode_cfg(uint32_t domain) |
| 896 | { |
| 897 | switch (domain) { |
| 898 | case RTD_DOMAIN: |
| 899 | return sizeof(struct upwr_power_mode_cfg_t) + |
| 900 | (sizeof(struct upwr_switch_board_t)* |
| 901 | UPWR_PMC_SWT_WORDS) + |
| 902 | (sizeof(struct upwr_mem_switches_t)* |
| 903 | UPWR_PMC_MEM_WORDS) - |
| 904 | 2U * (sizeof(void *) - sizeof(swt_board_ptr_t)); |
| 905 | |
| 906 | /* fall through */ |
| 907 | case APD_DOMAIN: |
| 908 | return sizeof(struct ps_apd_pwr_mode_cfg_t) + |
| 909 | (sizeof(struct upwr_switch_board_t)* |
| 910 | UPWR_PMC_SWT_WORDS) + |
| 911 | (sizeof(struct upwr_mem_switches_t)* |
| 912 | UPWR_PMC_MEM_WORDS); |
| 913 | |
| 914 | /* fall through */ |
| 915 | default: |
| 916 | break; |
| 917 | } |
| 918 | |
| 919 | return 0; |
| 920 | } |
| 921 | |
| 922 | /*=************************************************************************* |
| 923 | * All configs |
| 924 | *=*************************************************************************/ |
| 925 | |
| 926 | /* LVD/HVD monitor config for a single domain */ |
| 927 | |
| 928 | /* Domain + AVD monitor config |
| 929 | * For RTD, mapped in mon_cfg.mon_hvd_en |
| 930 | * For APD, mapped temporarily in pad_cfg.pad_tqsleep |
| 931 | */ |
| 932 | typedef union upwr_mon_cfg_union_t { |
| 933 | volatile uint32_t R; |
| 934 | struct { |
| 935 | /* Original config, not change */ |
| 936 | volatile uint32_t rsrv_1 : 8; |
| 937 | /* DOM */ |
| 938 | volatile uint32_t dom_lvd_irq_ena : 1; |
| 939 | volatile uint32_t dom_lvd_rst_ena : 1; |
| 940 | volatile uint32_t dom_hvd_irq_ena : 1; |
| 941 | volatile uint32_t dom_hvd_rst_ena : 1; |
| 942 | volatile uint32_t dom_lvd_lvl : 4; |
| 943 | volatile uint32_t dom_lvd_ena : 1; |
| 944 | volatile uint32_t dom_hvd_ena : 1; |
| 945 | /* AVD */ |
| 946 | volatile uint32_t avd_lvd_irq_ena : 1; |
| 947 | volatile uint32_t avd_lvd_rst_ena : 1; |
| 948 | volatile uint32_t avd_hvd_irq_ena : 1; |
| 949 | volatile uint32_t avd_hvd_rst_ena : 1; |
| 950 | volatile uint32_t avd_lvd_lvl : 4; |
| 951 | volatile uint32_t avd_lvd_ena : 1; |
| 952 | volatile uint32_t avd_hvd_ena : 1; |
| 953 | } B; |
| 954 | } upwr_mon_cfg_t; |
| 955 | |
| 956 | /* Get the monitor config word from RAM (domaind and AVD) */ |
| 957 | static inline uint32_t get_mon_cfg(uint8_t dom, void *mode_cfg) |
| 958 | { |
| 959 | if (dom == RTD_DOMAIN) { |
| 960 | return ((struct ps_rtd_pwr_mode_cfg_t *)mode_cfg)->mon_cfg.mon_hvd_en; |
| 961 | } else { |
| 962 | return ((struct ps_apd_pwr_mode_cfg_t *)mode_cfg)->pad_cfg.pad_tqsleep; |
| 963 | } |
| 964 | } |
| 965 | |
| 966 | /* Set the monitor config word in RAM (domaind and AVD) */ |
| 967 | static inline void set_mon_cfg(uint8_t dom, void *mode_cfg, |
| 968 | upwr_mon_cfg_t mon_cfg) |
| 969 | { |
| 970 | uint32_t *cfg; |
| 971 | |
| 972 | if (dom == RTD_DOMAIN) { |
| 973 | cfg = (uint32_t *)&((struct ps_rtd_pwr_mode_cfg_t *)mode_cfg)->mon_cfg.mon_hvd_en; |
| 974 | } else { |
| 975 | cfg = (uint32_t *)&((struct ps_apd_pwr_mode_cfg_t *)mode_cfg)->pad_cfg.pad_tqsleep; |
| 976 | } |
| 977 | |
| 978 | *cfg = mon_cfg.R; |
| 979 | } |
| 980 | |
| 981 | #define PMIC_REG_VALID_TAG 0xAAU |
| 982 | |
| 983 | /** |
| 984 | * limit the max pmic register->value count to 8 |
| 985 | * each data cost 4 Bytes, totally 32 Bytes |
| 986 | */ |
| 987 | #define MAX_PMIC_REG_COUNT 0x8U |
| 988 | |
| 989 | /** |
| 990 | * the configuration structure for PMIC register setting |
| 991 | * |
| 992 | * @ tag: The TAG number to judge if the data is valid or not, valid tag is PMIC_REG_VALID_TAG |
| 993 | * @ power_mode : corresponding to each domain's power mode |
| 994 | * RTD refer to upwr_ps_rtd_pwr_mode_t |
| 995 | * APD refer to abs_pwr_mode_t |
| 996 | * @ i2c_addr : i2c address |
| 997 | * @ i2c_data : i2c data value |
| 998 | */ |
| 999 | struct ps_pmic_reg_data_cfg_t { |
| 1000 | uint32_t tag : 8; |
| 1001 | uint32_t power_mode : 8; |
| 1002 | uint32_t i2c_addr : 8; |
| 1003 | uint32_t i2c_data : 8; |
| 1004 | }; |
| 1005 | |
| 1006 | /* Uniformize access to PMIC cfg for RTD and APD */ |
| 1007 | |
| 1008 | typedef union { |
| 1009 | struct upwr_reg_cfg_t RTD; |
| 1010 | struct upwr_pmic_cfg_t APD; |
| 1011 | } pmic_cfg_t; |
| 1012 | |
| 1013 | /* Access to PMIC mode mask and AVD mode */ |
| 1014 | |
| 1015 | typedef union { |
| 1016 | uint32_t R; |
| 1017 | struct { |
| 1018 | uint8_t mode; /* Domain PMIC mode */ |
| 1019 | uint8_t msk; /* Domain PMIC mode mask */ |
| 1020 | uint8_t avd_mode; /* AVD PMIC mode */ |
| 1021 | uint8_t avd_msk; /* AVD PMIC mode mask */ |
| 1022 | } B; |
| 1023 | } pmic_mode_cfg_t; |
| 1024 | |
| 1025 | /* Access RTD, APD and AVD modes and masks */ |
| 1026 | static inline pmic_mode_cfg_t *get_pmic_mode_cfg(uint8_t dom, pmic_cfg_t *cfg) |
| 1027 | { |
| 1028 | uint32_t *mode_cfg; |
| 1029 | |
| 1030 | if (dom == RTD_DOMAIN) { |
| 1031 | mode_cfg = &cfg->RTD.mode; |
| 1032 | } else { |
| 1033 | mode_cfg = &cfg->APD.mode; |
| 1034 | } |
| 1035 | |
| 1036 | return (pmic_mode_cfg_t *)mode_cfg; |
| 1037 | } |
| 1038 | |
| 1039 | static inline uint8_t get_pmic_mode(uint8_t dom, pmic_cfg_t *cfg) |
| 1040 | { |
| 1041 | return get_pmic_mode_cfg(dom, cfg)->B.mode; |
| 1042 | } |
| 1043 | |
| 1044 | static inline void set_pmic_mode(uint8_t dom, pmic_cfg_t *cfg, uint8_t mode) |
| 1045 | { |
| 1046 | get_pmic_mode_cfg(dom, cfg)->B.mode = mode; |
| 1047 | } |
| 1048 | |
| 1049 | static inline uint32_t get_pmic_mode_msk(uint8_t dom, pmic_cfg_t *cfg) |
| 1050 | { |
| 1051 | pmic_mode_cfg_t *mode_cfg; |
| 1052 | |
| 1053 | if (dom == RTD_DOMAIN) { |
| 1054 | mode_cfg = (pmic_mode_cfg_t *)&cfg->RTD.mode; |
| 1055 | return mode_cfg->B.msk; |
| 1056 | } else { |
| 1057 | return cfg->APD.mode_msk; |
| 1058 | } |
| 1059 | } |
| 1060 | |
| 1061 | /* Getters and setters for AVD mode and mask */ |
| 1062 | static inline uint8_t get_avd_pmic_mode(uint8_t dom, pmic_cfg_t *cfg) |
| 1063 | { |
| 1064 | return get_pmic_mode_cfg(dom, cfg)->B.avd_mode; |
| 1065 | } |
| 1066 | |
| 1067 | static inline void set_avd_pmic_mode(uint8_t dom, pmic_cfg_t *cfg, uint8_t mode) |
| 1068 | { |
| 1069 | get_pmic_mode_cfg(dom, cfg)->B.avd_mode = mode; |
| 1070 | } |
| 1071 | |
| 1072 | static inline uint8_t get_avd_pmic_mode_msk(uint8_t dom, pmic_cfg_t *cfg) |
| 1073 | { |
| 1074 | return get_pmic_mode_cfg(dom, cfg)->B.avd_msk; |
| 1075 | } |
| 1076 | |
| 1077 | static inline void set_avd_pmic_mode_msk(uint8_t dom, |
| 1078 | pmic_cfg_t *cfg, |
| 1079 | uint8_t msk) |
| 1080 | { |
| 1081 | get_pmic_mode_cfg(dom, cfg)->B.avd_msk = msk; |
| 1082 | } |
| 1083 | |
| 1084 | struct ps_delay_cfg_t { |
| 1085 | uint32_t tag : 8U; |
| 1086 | uint32_t rsv : 8U; |
| 1087 | uint32_t exitdelay : 16U; // exit delay in us |
| 1088 | }; |
| 1089 | |
| 1090 | #define PS_DELAY_TAG 0xA5U |
| 1091 | |
| 1092 | /* max exit delay = 0xffff = 65535 us = 65.5 ms (it is enough...) */ |
| 1093 | /* with 8 bits, 256 -> not enough */ |
| 1094 | |
| 1095 | typedef struct ps_delay_cfg_t ps_rtd_delay_cfgs_t[NUM_RTD_PWR_MODES]; |
| 1096 | typedef struct ps_delay_cfg_t ps_apd_delay_cfgs_t[NUM_APD_PWR_MODES]; |
| 1097 | |
| 1098 | typedef struct ps_rtd_pwr_mode_cfg_t ps_rtd_pwr_mode_cfgs_t[NUM_RTD_PWR_MODES]; |
| 1099 | typedef struct ps_apd_pwr_mode_cfg_t ps_apd_pwr_mode_cfgs_t[NUM_APD_PWR_MODES]; |
| 1100 | typedef struct ps_pmic_reg_data_cfg_t ps_rtd_pmic_reg_data_cfgs_t[MAX_PMIC_REG_COUNT]; |
| 1101 | typedef struct ps_pmic_reg_data_cfg_t ps_apd_pmic_reg_data_cfgs_t[MAX_PMIC_REG_COUNT]; |
| 1102 | |
| 1103 | struct ps_pwr_mode_cfg_t { |
| 1104 | ps_rtd_pwr_mode_cfgs_t ps_rtd_pwr_mode_cfg; |
| 1105 | ps_rtd_swt_cfgs_t ps_rtd_swt_cfg; |
| 1106 | ps_apd_pwr_mode_cfgs_t ps_apd_pwr_mode_cfg; |
| 1107 | ps_apd_swt_cfgs_t ps_apd_swt_cfg; |
| 1108 | ps_rtd_pmic_reg_data_cfgs_t ps_rtd_pmic_reg_data_cfg; |
| 1109 | ps_apd_pmic_reg_data_cfgs_t ps_apd_pmic_reg_data_cfg; |
| 1110 | ps_rtd_delay_cfgs_t ps_rtd_delay_cfg; |
| 1111 | ps_apd_delay_cfgs_t ps_apd_delay_cfg; |
| 1112 | |
| 1113 | }; |
| 1114 | |
| 1115 | #define UPWR_XCP_MIN_ADDR (0x28350000U) |
| 1116 | #define UPWR_XCP_MAX_ADDR (0x2836FFFCU) |
| 1117 | |
| 1118 | struct upwr_reg_access_t { |
| 1119 | uint32_t addr; |
| 1120 | uint32_t data; |
| 1121 | uint32_t mask; /* mask=0 commands read */ |
| 1122 | }; |
| 1123 | |
| 1124 | typedef upwr_pointer_msg upwr_xcp_access_msg; |
| 1125 | |
| 1126 | /* unions for the shared memory buffer */ |
| 1127 | |
| 1128 | typedef union { |
| 1129 | struct upwr_reg_access_t reg_access; |
| 1130 | } upwr_xcp_union_t; |
| 1131 | |
| 1132 | typedef union { |
| 1133 | struct { |
| 1134 | struct ps_rtd_pwr_mode_cfg_t rtd_struct; |
| 1135 | struct upwr_switch_board_t rtd_switch; |
| 1136 | struct upwr_mem_switches_t rtd_memory; |
| 1137 | } rtd_pwr_mode; |
| 1138 | struct { |
| 1139 | struct ps_apd_pwr_mode_cfg_t apd_struct; |
| 1140 | struct upwr_switch_board_t apd_switch; |
| 1141 | struct upwr_mem_switches_t apd_memory; |
| 1142 | } apd_pwr_mode; |
| 1143 | } upwr_pwm_union_t; |
| 1144 | |
| 1145 | #define MAX_SG_EXCEPT_MEM_SIZE sizeof(upwr_xcp_union_t) |
| 1146 | #define MAX_SG_PWRMGMT_MEM_SIZE sizeof(upwr_pwm_union_t) |
| 1147 | |
| 1148 | /** |
| 1149 | * VOLTM group need shared memory for PMIC IC configuration |
| 1150 | * 256 Bytes is enough for PMIC register array |
| 1151 | */ |
| 1152 | #define MAX_SG_VOLTM_MEM_SIZE 256U |
| 1153 | |
| 1154 | #endif /* UPWR_SOC_DEFS_H */ |