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Bai Ping06e325e2018-10-28 00:12:34 +08001/*
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05002 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Bai Ping06e325e2018-10-28 00:12:34 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
Bai Ping06e325e2018-10-28 00:12:34 +08009#include <console_macros.S>
10#include <assert_macros.S>
11#include "imx_uart.h"
12
13#define URXD 0x0 /* Receiver Register */
14#define UTXD 0x40 /* Transmitter Register */
Loic Poulain311b33d2023-01-11 16:08:48 +010015#define USR2 0x98 /* UART Status Register 2 */
Bai Ping06e325e2018-10-28 00:12:34 +080016#define UTS 0xb4 /* UART Test Register (mx31) */
17#define URXD_RX_DATA (0xFF)
18
Anson Huang1fc11bd2019-01-15 14:27:10 +080019 .globl console_imx_uart_register
20 .globl console_imx_uart_init
21 .globl console_imx_uart_putc
22 .globl console_imx_uart_getc
23 .globl console_imx_uart_flush
Bai Ping06e325e2018-10-28 00:12:34 +080024
25func console_imx_uart_register
26 mov x7, x30
27 mov x6, x3
28 cbz x6, register_fail
Andre Przywaraab269202020-03-05 13:56:56 +000029 str x0, [x6, #CONSOLE_T_BASE]
Bai Ping06e325e2018-10-28 00:12:34 +080030
31 bl console_imx_uart_init
32 cbz x0, register_fail
33
34 mov x0, x6
35 mov x30, x7
Sandrine Bailleuxf57e2032023-10-11 08:38:00 +020036 finish_console_register imx_uart putc=1, getc=ENABLE_CONSOLE_GETC, flush=1
Bai Ping06e325e2018-10-28 00:12:34 +080037
38register_fail:
39 ret x7
40endfunc console_imx_uart_register
41
42func console_imx_uart_init
43 mov w0, #1
44 ret
45endfunc console_imx_uart_init
46
47func console_imx_uart_putc
Andre Przywaraab269202020-03-05 13:56:56 +000048 ldr x1, [x1, #CONSOLE_T_BASE]
Bai Ping06e325e2018-10-28 00:12:34 +080049 cbz x1, putc_error
50
51 /* Prepare '\r' to '\n' */
52 cmp w0, #0xA
53 b.ne 2f
541:
55 /* Check if the transmit FIFO is full */
56 ldr w2, [x1, #UTS]
Loic Poulain311b33d2023-01-11 16:08:48 +010057 tbnz w2, #4, 1b
Bai Ping06e325e2018-10-28 00:12:34 +080058 mov w2, #0xD
59 str w2, [x1, #UTXD]
602:
61 /* Check if the transmit FIFO is full */
62 ldr w2, [x1, #UTS]
Loic Poulain311b33d2023-01-11 16:08:48 +010063 tbnz w2, #4, 2b
Bai Ping06e325e2018-10-28 00:12:34 +080064 str w0, [x1, #UTXD]
65 ret
66putc_error:
67 mov w0, #-1
68 ret
69endfunc console_imx_uart_putc
70
71func console_imx_uart_getc
Andre Przywaraab269202020-03-05 13:56:56 +000072 ldr x0, [x0, #CONSOLE_T_BASE]
Bai Ping06e325e2018-10-28 00:12:34 +080073 cbz x0, getc_error
741:
75 ldr w1, [x0, #UTS]
76 tbnz w1, #5, 1b
77
78 ldr w1, [x0, #URXD]
79 and w0, w1, #URXD_RX_DATA
80
81 ret
82getc_error:
83 mov w0, #-1
84 ret
85endfunc console_imx_uart_getc
Anson Huang1fc11bd2019-01-15 14:27:10 +080086
87func console_imx_uart_flush
Loic Poulain311b33d2023-01-11 16:08:48 +010088 ldr x0, [x0, #CONSOLE_T_BASE]
89 cbz x0, flush_exit
901:
91 /* Wait for the transmit complete bit */
92 ldr w1, [x0, #USR2]
93 tbz w1, #3, 1b
94
95flush_exit:
Anson Huang1fc11bd2019-01-15 14:27:10 +080096 ret
97endfunc console_imx_uart_flush