| Chia-Wei Wang | a7556d8 | 2022-11-02 17:50:21 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023, Aspeed Technology Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <asm_macros.S> |
| 8 | #include <assert_macros.S> |
| 9 | #include <arch.h> |
| 10 | #include <cortex_a35.h> |
| 11 | #include <platform_def.h> |
| 12 | |
| Chia-Wei Wang | a741460 | 2023-09-27 13:51:04 +0800 | [diff] [blame] | 13 | .globl platform_mem_init |
| Chia-Wei Wang | a7556d8 | 2022-11-02 17:50:21 +0800 | [diff] [blame] | 14 | .globl plat_is_my_cpu_primary |
| 15 | .globl plat_my_core_pos |
| 16 | .globl plat_secondary_cold_boot_setup |
| 17 | .globl plat_get_syscnt_freq2 |
| 18 | .globl plat_crash_console_init |
| 19 | .globl plat_crash_console_putc |
| 20 | .globl plat_crash_console_flush |
| 21 | |
| Chia-Wei Wang | a741460 | 2023-09-27 13:51:04 +0800 | [diff] [blame] | 22 | /* void platform_mem_init(void); */ |
| 23 | func platform_mem_init |
| 24 | /* DRAM init. is done by preceding MCU */ |
| 25 | ret |
| 26 | endfunc platform_mem_init |
| 27 | |
| Chia-Wei Wang | a7556d8 | 2022-11-02 17:50:21 +0800 | [diff] [blame] | 28 | /* unsigned int plat_is_my_cpu_primary(void); */ |
| 29 | func plat_is_my_cpu_primary |
| 30 | mrs x0, mpidr_el1 |
| 31 | and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) |
| 32 | cmp x0, #PLATFORM_CORE_PRIMARY |
| 33 | cset w0, eq |
| 34 | ret |
| 35 | endfunc plat_is_my_cpu_primary |
| 36 | |
| 37 | /* unsigned int plat_my_core_pos(void); */ |
| 38 | func plat_my_core_pos |
| 39 | mrs x0, mpidr_el1 |
| 40 | mov x2, #PLATFORM_CORE_COUNT_PER_CLUSTER |
| 41 | and x1, x0, #MPIDR_CPU_MASK |
| 42 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 43 | madd x0, x0, x2, x1 |
| 44 | ret |
| 45 | endfunc plat_my_core_pos |
| 46 | |
| Chia-Wei Wang | a741460 | 2023-09-27 13:51:04 +0800 | [diff] [blame] | 47 | /* void plat_secondary_cold_boot_setup (void); */ |
| 48 | func plat_secondary_cold_boot_setup |
| 49 | mov x0, xzr |
| 50 | bl plat_my_core_pos |
| 51 | mov_imm x1, SCU_CPU_SMP_EP0 |
| 52 | add x1, x1, x0, lsl #3 |
| 53 | |
| 54 | poll_smp_mbox_go: |
| 55 | wfe |
| 56 | ldr x0, [x1] |
| 57 | cmp x0, xzr |
| 58 | beq poll_smp_mbox_go |
| 59 | br x0 |
| 60 | endfunc plat_secondary_cold_boot_setup |
| 61 | |
| Chia-Wei Wang | a7556d8 | 2022-11-02 17:50:21 +0800 | [diff] [blame] | 62 | /* unsigned int plat_get_syscnt_freq2(void); */ |
| 63 | func plat_get_syscnt_freq2 |
| 64 | mov_imm w0, PLAT_SYSCNT_CLKIN_HZ |
| 65 | ret |
| 66 | endfunc plat_get_syscnt_freq2 |
| 67 | |
| 68 | /* int plat_crash_console_init(void); */ |
| 69 | func plat_crash_console_init |
| 70 | mov_imm x0, CONSOLE_UART_BASE |
| 71 | mov_imm x1, CONSOLE_UART_CLKIN_HZ |
| 72 | mov_imm x2, CONSOLE_UART_BAUDRATE |
| 73 | b console_16550_core_init |
| 74 | endfunc plat_crash_console_init |
| 75 | |
| 76 | /* int plat_crash_console_putc(int); */ |
| 77 | func plat_crash_console_putc |
| 78 | mov_imm x1, CONSOLE_UART_BASE |
| 79 | b console_16550_core_putc |
| 80 | endfunc plat_crash_console_putc |
| 81 | |
| 82 | /* void plat_crash_console_flush(void); */ |
| 83 | func plat_crash_console_flush |
| 84 | mov_imm x0, CONSOLE_UART_BASE |
| 85 | b console_16550_core_flush |
| 86 | endfunc plat_crash_console_flush |