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Aditya Angadicdd7f632020-04-06 17:11:23 +05301/*
Rohit Mathew20d4a212024-02-03 21:20:17 +00002 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
Aditya Angadicdd7f632020-04-06 17:11:23 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Aditya Angadiac0e0d32021-02-17 18:46:22 +05307#include <common/debug.h>
8#include <plat/arm/common/plat_arm.h>
9#include <platform_def.h>
10
11/* TZC memory regions for the first chip */
12static const arm_tzc_regions_info_t tzc_regions[] = {
13 ARM_TZC_REGIONS_DEF,
14 {}
15};
16
Rohit Mathew644d9e22024-02-03 19:06:16 +000017#if NRD_CHIP_COUNT > 1
18static const arm_tzc_regions_info_t tzc_regions_mc[][NRD_CHIP_COUNT - 1] = {
Aditya Angadiac0e0d32021-02-17 18:46:22 +053019 {
20 /* TZC memory regions for second chip */
Rohit Mathew6521c1d2024-02-03 22:23:25 +000021 NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
Aditya Angadiac0e0d32021-02-17 18:46:22 +053022 {}
23 },
Rohit Mathew644d9e22024-02-03 19:06:16 +000024#if NRD_CHIP_COUNT > 2
Aditya Angadiac0e0d32021-02-17 18:46:22 +053025 {
26 /* TZC memory regions for third chip */
Rohit Mathew6521c1d2024-02-03 22:23:25 +000027 NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
Aditya Angadiac0e0d32021-02-17 18:46:22 +053028 {}
29 },
30#endif
Rohit Mathew644d9e22024-02-03 19:06:16 +000031#if NRD_CHIP_COUNT > 3
Aditya Angadiac0e0d32021-02-17 18:46:22 +053032 {
33 /* TZC memory regions for fourth chip */
Rohit Mathew6521c1d2024-02-03 22:23:25 +000034 NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
Aditya Angadiac0e0d32021-02-17 18:46:22 +053035 {}
36 },
37#endif
38};
Rohit Mathew644d9e22024-02-03 19:06:16 +000039#endif /* NRD_CHIP_COUNT */
Aditya Angadiac0e0d32021-02-17 18:46:22 +053040
Aditya Angadicdd7f632020-04-06 17:11:23 +053041/* Initialize the secure environment */
42void plat_arm_security_setup(void)
43{
Aditya Angadiac0e0d32021-02-17 18:46:22 +053044 unsigned int i;
45
46 INFO("Configuring TrustZone Controller for Chip 0\n");
47
48 for (i = 0; i < TZC400_COUNT; i++) {
49 arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
50 }
51
Rohit Mathew644d9e22024-02-03 19:06:16 +000052#if NRD_CHIP_COUNT > 1
Aditya Angadiac0e0d32021-02-17 18:46:22 +053053 unsigned int j;
54
Rohit Mathew644d9e22024-02-03 19:06:16 +000055 for (i = 1; i < NRD_CHIP_COUNT; i++) {
Aditya Angadiac0e0d32021-02-17 18:46:22 +053056 INFO("Configuring TrustZone Controller for Chip %u\n", i);
57
58 for (j = 0; j < TZC400_COUNT; j++) {
Rohit Mathewaac0c3c2024-02-03 22:16:14 +000059 arm_tzc400_setup(NRD_REMOTE_CHIP_MEM_OFFSET(i)
Aditya Angadiac0e0d32021-02-17 18:46:22 +053060 + TZC400_BASE(j), tzc_regions_mc[i-1]);
61 }
62 }
63#endif
Aditya Angadicdd7f632020-04-06 17:11:23 +053064}