Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 1 | /* |
Tamas Ban | 43e0d92 | 2023-05-08 13:41:29 +0200 | [diff] [blame] | 2 | * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | |
| 9 | #include <platform_def.h> |
| 10 | |
| 11 | #include <common/bl_common.h> |
| 12 | #include <common/debug.h> |
| 13 | #include <drivers/arm/ccn.h> |
Tamas Ban | 43e0d92 | 2023-05-08 13:41:29 +0200 | [diff] [blame] | 14 | #include <drivers/arm/css/sds.h> |
| 15 | #include <lib/utils_def.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 16 | #include <plat/arm/common/plat_arm.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <plat/common/platform.h> |
Aditya Angadi | 20b4841 | 2019-04-16 11:29:14 +0530 | [diff] [blame] | 18 | #include <drivers/arm/sbsa.h> |
Rohit Mathew | a0dd307 | 2024-02-03 17:22:54 +0000 | [diff] [blame] | 19 | |
| 20 | #include <nrd_base_platform_def.h> |
Olivier Deprez | 21cf360 | 2020-07-30 17:18:33 +0200 | [diff] [blame] | 21 | |
| 22 | #if SPM_MM |
Paul Beesley | 45f4028 | 2019-10-15 10:57:42 +0000 | [diff] [blame] | 23 | #include <services/spm_mm_partition.h> |
Olivier Deprez | 21cf360 | 2020-07-30 17:18:33 +0200 | [diff] [blame] | 24 | #endif |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 25 | |
Rohit Mathew | 6521c1d | 2024-02-03 22:23:25 +0000 | [diff] [blame] | 26 | #define NRD_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 27 | V2M_FLASH0_SIZE, \ |
| 28 | MT_DEVICE | MT_RO | MT_SECURE) |
| 29 | /* |
| 30 | * Table of regions for different BL stages to map using the MMU. |
| 31 | * This doesn't include Trusted RAM as the 'mem_layout' argument passed to |
| 32 | * arm_configure_mmu_elx() will give the available subset of that. |
| 33 | * |
| 34 | * Replace or extend the below regions as required |
| 35 | */ |
| 36 | #if IMAGE_BL1 |
| 37 | const mmap_region_t plat_arm_mmap[] = { |
| 38 | ARM_MAP_SHARED_RAM, |
Rohit Mathew | 6521c1d | 2024-02-03 22:23:25 +0000 | [diff] [blame] | 39 | NRD_MAP_FLASH0_RO, |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame] | 40 | NRD_MAP_DEVICE, |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 41 | SOC_CSS_MAP_DEVICE, |
| 42 | {0} |
| 43 | }; |
| 44 | #endif |
| 45 | #if IMAGE_BL2 |
| 46 | const mmap_region_t plat_arm_mmap[] = { |
| 47 | ARM_MAP_SHARED_RAM, |
Rohit Mathew | 6521c1d | 2024-02-03 22:23:25 +0000 | [diff] [blame] | 48 | NRD_MAP_FLASH0_RO, |
Sami Mujawar | a4f315c | 2020-04-30 15:50:34 +0100 | [diff] [blame] | 49 | #ifdef PLAT_ARM_MEM_PROT_ADDR |
| 50 | ARM_V2M_MAP_MEM_PROTECT, |
| 51 | #endif |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame] | 52 | NRD_MAP_DEVICE, |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 53 | SOC_CSS_MAP_DEVICE, |
| 54 | ARM_MAP_NS_DRAM1, |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 55 | #if NRD_CHIP_COUNT > 1 |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame] | 56 | NRD_MAP_DEVICE_REMOTE_CHIP(1), |
Aditya Angadi | ca14fb8 | 2021-02-17 18:39:32 +0530 | [diff] [blame] | 57 | #endif |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 58 | #if NRD_CHIP_COUNT > 2 |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame] | 59 | NRD_MAP_DEVICE_REMOTE_CHIP(2), |
Aditya Angadi | ca14fb8 | 2021-02-17 18:39:32 +0530 | [diff] [blame] | 60 | #endif |
Rohit Mathew | 644d9e2 | 2024-02-03 19:06:16 +0000 | [diff] [blame] | 61 | #if NRD_CHIP_COUNT > 3 |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame] | 62 | NRD_MAP_DEVICE_REMOTE_CHIP(3), |
Aditya Angadi | ca14fb8 | 2021-02-17 18:39:32 +0530 | [diff] [blame] | 63 | #endif |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 64 | #if ARM_BL31_IN_DRAM |
| 65 | ARM_MAP_BL31_SEC_DRAM, |
| 66 | #endif |
Paul Beesley | fe975b4 | 2019-09-16 11:29:03 +0000 | [diff] [blame] | 67 | #if SPM_MM |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 68 | ARM_SP_IMAGE_MMAP, |
| 69 | #endif |
Arvind Ram Prakash | 11b9b49 | 2022-11-22 14:41:00 -0600 | [diff] [blame] | 70 | #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2 |
John Tsichritzis | 0c6ee74 | 2018-08-22 12:36:37 +0100 | [diff] [blame] | 71 | ARM_MAP_BL1_RW, |
| 72 | #endif |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 73 | {0} |
| 74 | }; |
| 75 | #endif |
| 76 | #if IMAGE_BL31 |
| 77 | const mmap_region_t plat_arm_mmap[] = { |
| 78 | ARM_MAP_SHARED_RAM, |
| 79 | V2M_MAP_IOFPGA, |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame] | 80 | NRD_MAP_DEVICE, |
Sami Mujawar | a4f315c | 2020-04-30 15:50:34 +0100 | [diff] [blame] | 81 | #ifdef PLAT_ARM_MEM_PROT_ADDR |
| 82 | ARM_V2M_MAP_MEM_PROTECT, |
| 83 | #endif |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 84 | SOC_CSS_MAP_DEVICE, |
Paul Beesley | fe975b4 | 2019-09-16 11:29:03 +0000 | [diff] [blame] | 85 | #if SPM_MM |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 86 | ARM_SPM_BUF_EL3_MMAP, |
| 87 | #endif |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 88 | {0} |
| 89 | }; |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 90 | |
Paul Beesley | fe975b4 | 2019-09-16 11:29:03 +0000 | [diff] [blame] | 91 | #if SPM_MM && defined(IMAGE_BL31) |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 92 | const mmap_region_t plat_arm_secure_partition_mmap[] = { |
Thomas Abraham | e4030c0 | 2021-02-15 14:14:59 +0530 | [diff] [blame] | 93 | PLAT_ARM_SECURE_MAP_SYSTEMREG, |
| 94 | PLAT_ARM_SECURE_MAP_NOR2, |
Rohit Mathew | 9c07f60 | 2021-12-13 15:33:04 +0000 | [diff] [blame] | 95 | SOC_PLATFORM_SECURE_UART, |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 96 | PLAT_ARM_SECURE_MAP_DEVICE, |
| 97 | ARM_SP_IMAGE_MMAP, |
| 98 | ARM_SP_IMAGE_NS_BUF_MMAP, |
Manish Pandey | f90a73c | 2023-10-10 15:42:19 +0100 | [diff] [blame] | 99 | #if ENABLE_FEAT_RAS && FFH_SUPPORT |
Rohit Mathew | aac0c3c | 2024-02-03 22:16:14 +0000 | [diff] [blame] | 100 | NRD_SP_CPER_BUF_MMAP, |
Thomas Abraham | a0aea1a | 2021-02-16 11:36:00 +0530 | [diff] [blame] | 101 | #endif |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 102 | ARM_SP_IMAGE_RW_MMAP, |
| 103 | ARM_SPM_BUF_EL0_MMAP, |
| 104 | {0} |
| 105 | }; |
Paul Beesley | fe975b4 | 2019-09-16 11:29:03 +0000 | [diff] [blame] | 106 | #endif /* SPM_MM && defined(IMAGE_BL31) */ |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 107 | #endif |
| 108 | |
| 109 | ARM_CASSERT_MMAP |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 110 | |
Paul Beesley | fe975b4 | 2019-09-16 11:29:03 +0000 | [diff] [blame] | 111 | #if SPM_MM && defined(IMAGE_BL31) |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 112 | /* |
| 113 | * Boot information passed to a secure partition during initialisation. Linear |
| 114 | * indices in MP information will be filled at runtime. |
| 115 | */ |
Paul Beesley | 45f4028 | 2019-10-15 10:57:42 +0000 | [diff] [blame] | 116 | static spm_mm_mp_info_t sp_mp_info[] = { |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 117 | [0] = {0x81000000, 0}, |
| 118 | [1] = {0x81000100, 0}, |
| 119 | [2] = {0x81000200, 0}, |
| 120 | [3] = {0x81000300, 0}, |
| 121 | [4] = {0x81010000, 0}, |
| 122 | [5] = {0x81010100, 0}, |
| 123 | [6] = {0x81010200, 0}, |
| 124 | [7] = {0x81010300, 0}, |
| 125 | }; |
| 126 | |
Paul Beesley | 45f4028 | 2019-10-15 10:57:42 +0000 | [diff] [blame] | 127 | const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 128 | .h.type = PARAM_SP_IMAGE_BOOT_INFO, |
| 129 | .h.version = VERSION_1, |
Paul Beesley | 45f4028 | 2019-10-15 10:57:42 +0000 | [diff] [blame] | 130 | .h.size = sizeof(spm_mm_boot_info_t), |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 131 | .h.attr = 0, |
| 132 | .sp_mem_base = ARM_SP_IMAGE_BASE, |
| 133 | .sp_mem_limit = ARM_SP_IMAGE_LIMIT, |
| 134 | .sp_image_base = ARM_SP_IMAGE_BASE, |
| 135 | .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, |
| 136 | .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, |
Ard Biesheuvel | 8b034fc | 2018-12-29 19:43:21 +0100 | [diff] [blame] | 137 | .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 138 | .sp_shared_buf_base = PLAT_SPM_BUF_BASE, |
| 139 | .sp_image_size = ARM_SP_IMAGE_SIZE, |
| 140 | .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, |
| 141 | .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, |
Ard Biesheuvel | 8b034fc | 2018-12-29 19:43:21 +0100 | [diff] [blame] | 142 | .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 143 | .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, |
| 144 | .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, |
| 145 | .num_cpus = PLATFORM_CORE_COUNT, |
| 146 | .mp_info = &sp_mp_info[0], |
| 147 | }; |
| 148 | |
| 149 | const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) |
| 150 | { |
| 151 | return plat_arm_secure_partition_mmap; |
| 152 | } |
| 153 | |
Paul Beesley | 45f4028 | 2019-10-15 10:57:42 +0000 | [diff] [blame] | 154 | const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 155 | void *cookie) |
| 156 | { |
| 157 | return &plat_arm_secure_partition_boot_info; |
| 158 | } |
Paul Beesley | fe975b4 | 2019-09-16 11:29:03 +0000 | [diff] [blame] | 159 | #endif /* SPM_MM && defined(IMAGE_BL31) */ |
John Tsichritzis | 0c6ee74 | 2018-08-22 12:36:37 +0100 | [diff] [blame] | 160 | |
Antonio Nino Diaz | 9b75986 | 2018-09-25 11:38:18 +0100 | [diff] [blame] | 161 | #if TRUSTED_BOARD_BOOT |
John Tsichritzis | 0c6ee74 | 2018-08-22 12:36:37 +0100 | [diff] [blame] | 162 | int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) |
| 163 | { |
| 164 | assert(heap_addr != NULL); |
| 165 | assert(heap_size != NULL); |
| 166 | |
| 167 | return arm_get_mbedtls_heap(heap_addr, heap_size); |
| 168 | } |
| 169 | #endif |
Aditya Angadi | 20b4841 | 2019-04-16 11:29:14 +0530 | [diff] [blame] | 170 | |
| 171 | void plat_arm_secure_wdt_start(void) |
| 172 | { |
| 173 | sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT); |
| 174 | } |
| 175 | |
| 176 | void plat_arm_secure_wdt_stop(void) |
| 177 | { |
| 178 | sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE); |
| 179 | } |
Tamas Ban | 43e0d92 | 2023-05-08 13:41:29 +0200 | [diff] [blame] | 180 | |
Rohit Mathew | 0ec6ed9 | 2024-02-03 18:39:10 +0000 | [diff] [blame] | 181 | static sds_region_desc_t nrd_sds_regions[] = { |
Tamas Ban | 43e0d92 | 2023-05-08 13:41:29 +0200 | [diff] [blame] | 182 | { .base = PLAT_ARM_SDS_MEM_BASE }, |
| 183 | }; |
| 184 | |
| 185 | sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count) |
| 186 | { |
Rohit Mathew | 0ec6ed9 | 2024-02-03 18:39:10 +0000 | [diff] [blame] | 187 | *region_count = ARRAY_SIZE(nrd_sds_regions); |
Tamas Ban | 43e0d92 | 2023-05-08 13:41:29 +0200 | [diff] [blame] | 188 | |
Rohit Mathew | 0ec6ed9 | 2024-02-03 18:39:10 +0000 | [diff] [blame] | 189 | return nrd_sds_regions; |
Tamas Ban | 43e0d92 | 2023-05-08 13:41:29 +0200 | [diff] [blame] | 190 | } |